HC705MC4GRSSLASHD datasheet(75/180 Pages) NXP

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Analog Subsystem

A/D Status and Control Register

General Release Specification

Analog Subsystem

8.6 A/D Status and Control Register

The following paragraphs describe the function of the A/D status and

control register.

COCO — Conversions Complete

This read-only status bit is set when a conversion is completed,

indicating that the A/D data register contains valid results. This bit is

cleared whenever the A/D status and control register is written and a

new conversion is automatically started or whenever the A/D data

A/D status and control register, conversions of the selected channel

will continue every 32 cycles until the A/D status and control register

is written again. In this continuous conversion mode, the A/D data

cycles. Data from the previous conversion will be overwritten

regardless of the state of the COCO bit prior to writing.

ADRC — A/D RC Oscillator Control

When the RC oscillator is selected (ADRC = 1) to be the A/D clock

source, it requires a time, tADRC, to stabilize. Results can be

inaccurate during this time. If the CPU clock is running below 1 Mhz,

the RC oscillator must be used.

When ADRC = 0, the A/D uses the CPU clock.

Address:

$0025

Bit 7

654321

Bit 0

Read:

COCO

ADRC

ADON

CH3

CH2

CH1

CH0

Write:

Reset:

00000000

= Unimplemented

Figure 8-2. A/D Status and Control Register (ADSCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D Datasheet(PDF) 75 Page - NXP Semiconductors

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