HC705MC4GRSSLASHD datasheet(87/180 Pages) NXP

87 / 180 page

16-Bit Timer

Input Capture

General Release Specification

16-Bit Timer

9.5 Input Capture

Registers are used to latch the value of the free-running counter after a

defined transition is sensed by the input capture edge detector (

Note:

The input capture edge detector contains a Schmitt trigger to improve

noise immunity.) The edge that triggers the counter transfer is defined

by each input edge bit (IEDG1, IEDG2) in register TCR. Dynamically

changing from Capture to Compare function will not affect the contents

of the registers. All of the bits in the Input Capture register pair ICRH /

ICRL are readable and are not altered by the 16-bit timer’s control logic.

Writes have no effect. Reset does not affect the contents of these

registers. See Figure 9-8 and Figure 9-9.

Address:

$001B

Bit 7

654321

Bit 0

Read:

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

Write:

Reset:

Unaffected by Reset

Address:

$001C

Bit 7

654321

Bit 0

Read:

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Write:

Reset:

Unaffected by Reset

= Unimplemented

Figure 9-8. Input Capture Registers (ICRH1/ICRL1)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D Datasheet(PDF) 87 Page - NXP Semiconductors

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