HC705MC4GRSSLASHD datasheet(105/180 Pages) NXP

105 / 180 page

Pulse Width Modulator

PWM Control Registers

General Release Specification

Pulse Width Modulator

10.4.3 UPDATE Register

Some applications cannot always wait until the end of the PWM cycle in

process before new control or data values take effect (for example,

during fault conditions). The UPDATEx bits provide a mechanism to

override the register interlock for these situations. The UPDATE register

is shown in Figure 10-10.

If the register interlock is satisfied and the corresponding update bit is

clear, the PWM registers are updated at the end of the current PWM

cycle. If the register interlock is satisfied and the corresponding update

bit is set the PWM registers are updated immediately. Figure 10-11

shows the different timing cases of applying the update condition and its

affects on PWM output.

After a RESET or subsequent to re-enabling the PWM channels, it is

necessary for the user to write to the data registers RATE, CTL-B (if

PWMB is used), and CTL-A (in that order) before writing to the UPDATE

PWMB (writing to CTL-A or CTL-B) may disable the PWM.

After disabling a PWM channel, the corresponding UPDATE bit must be

cleared before enabling the channel again. After clearing the

corresponding UPDATE bit, the sequence of writing to the RATE,

CTL-B, CTL-A, and then setting the corresponding UPDATE bit must be

followed before re-enabling the PWM channels.

Address:

$0027

Bit 7

654321

Bit 0

Read: UPDATE

UPDATE

Write:

Reset:

00000000

= Unimplemented

Figure 10-10. PWM Update Register (UPDATE)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D Datasheet(PDF) 105 Page - NXP Semiconductors