AMD-K6-2ESLASH233AMZ datasheet(296/332 Pages) AMD

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278

Signal Switching Characteristics

Chapter 15

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

15.9

RESET and Test Signal Timing

Table 62. RESET and Configuration Signals for 100-MHz Bus Operation

Symbol

Parameter Description

Preliminary Data

Figure

Min

Max

t90

RESET Setup Time

1.7 ns

t91

RESET Hold Time

1.0 ns

t92

RESET Pulse Width, VCC and CLK Stable

15 clocks

t93

RESET Active After VCC and CLK Stable

1.0 ms

t94

Notes:

1. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.

BF[2:0] Setup Time

1.0 ms

t95

BF[2:0] Hold Time

2 clocks

t96

intentionally left blank

t97

intentionally left blank

t98

intentionally left blank

t99

2. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET

is sampled negated.

FLUSH# Setup Time

1.7 ns

t100

FLUSH# Hold Time

1.0 ns

t101

3. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of

RESET.

FLUSH# Setup Time

2 clocks

t102

FLUSH# Hold Time

2 clocks

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