AMD-K6-2ESLASH233AMZ datasheet(36/332 Pages) AMD

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Internal Architecture

Chapter 2

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

Figure 5. AMD-K6™-2E Processor Scheduler

2.5

Execution Units

The AMD-K6-2E processor contains ten parallel execution

units —store, load, integer X ALU, integer Y ALU, MMX ALU

(X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU,

floating-point, and branch condition. Each unit is independent

and capable of handling the RISC86 operations. Table 1 on

page 19 details the execution units, functions performed within

these units, operation latency, and operation throughput.

The store and load execution units are two-stage pipelined

designs.

The store unit performs data writes and register calculation

for LEA/PUSH. Data memory and register writes from stores

are available after one clock. Store operations are held in a

store queue prior to execution. From there, they execute in

order.

The load unit performs data memory reads. Data is available

from the load unit after two clocks.

RISC86 Operation Buffer

RISC86 Issue Buses

RISC86 #0

RISC86 #1

RISC86 #2

RISC86 #3

Centralized RISC86®

Operation Scheduler

From Decode Logic

AMD-K6-2E/233AMZ Datasheet(PDF) 36 Page - Advanced Micro Devices