AMD-K6-2ESLASH233AMZ datasheet(31/332 Pages) AMD

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Chapter 2

Internal Architecture

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

burst read cycles occurring back-to-back or, if allowed, as

pipelined cycles.

The 3DNow! technology includes a new instruction named

PREFETCH that allows a cache line to be prefetched into the

data cache. The PREFETCH instruction format is defined in

Table 15, “3DNow!™ Instructions,” on page 81. For more

detailed information, see the 3DNow!™ Technology Manual,

order #21928.

Predecode Bits

Decoding x86 instructions is particularly difficult because the

instructions are variable in length (1 to 15 bytes). Predecode

logic supplies the five predecode bits associated with each

instruction byte. The predecode bits indicate the number of

bytes to the start of the next x86 instruction. The predecode

bits are stored in an extended instruction cache alongside each

x86 instruction byte, as shown in Figure 2 on page 12. The

predecode bits are passed with the instruction bytes to the

decoders where they assist with parallel x86 instruction

decoding.

2.3

Instruction Fetch and Decode

Instruction Fetch

The processor can fetch up to 16 bytes per clock out of the

instruction cache or branch ta rg et cache. The fetche d

information is placed into a 16-byte instruction buffer that

feeds directly into the decoders (see Figure 3 on page 14).

Fetching can occur along a single execution stream with up to

seven outstanding branches taken.

The instruction fetch logic is capable of retrieving any 16

contiguous bytes of information within a 32-byte boundary.

There is no additional penalty when the 16 bytes of instructions

lie across a cache line boundary. The instruction bytes are

loaded into the instruction buffer as they are consumed by the

decoders.

Although instructions can be consumed with byte granularity,

the instruction buffer is managed on a memory-aligned word

(two bytes) organization. Therefore, instructions are loaded and

replaced with word granularity. When a control transfer

occurs — such as a JMP instruction — the entire instruction

buffer is flushed and reloaded with a new set of 16 instruction

bytes.

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