AMD-K6-2ESLASH233AMZ datasheet(37/332 Pages) AMD

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Chapter 2

Internal Architecture

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Th e I n te ger X exec utio n unit c a n operat e on a ll AL U

operations, multiplies, divides (signed and unsigned), shifts,

and rotates.

The Integer Y execution unit can operate on the basic word and

doubleword ALU operations — ADD, AND, CMP, OR, SUB,

XOR, zero-extend, and sign-extend operands.

The func tional units that exec ut e MMX and 3DNow!

instructions share pipeline control with the Integer X and

Integer Y units.

Pipelines

The register X and Y functional units are attached to the issue

bus for the register X execution pipeline or the issue bus for the

has dedicated resources that consist of an integer execution

unit and an MMX ALU execution unit, therefore allowing

superscalar operation on integer and MMX instructions. In

addition, both the X and Y issue buses are connected to the

3DNow! ALU, the MMX/3DNow! multiplier, and MMX shifter,

which allows the appropriate RISC86 operation to be issued

through either bus. Figure 6 on page 20 shows the details of the

X and Y register pipelines.

Table 1. Execution Latency and Throughput of Execution Units

Functional Unit

Function

Latency

Throughput

Store

LEA/PUSH, Address (Pipelined)

Memory Store (Pipelined)

Load

Memory Loads (Pipelined)

Integer X

Integer ALU

Integer Multiply

2–3

Integer Shift

Multimedia

(processes

MMX instructions)

MMX ALU

MMX Shifts, Packs, Unpack

MMX Multiply

Integer Y

Basic ALU (16-bit and 32-bit operands)

Branch

Resolves Branch Conditions

FPU

FADD, FSUB, FMUL

3DNow!

3DNow! ALU

3DNow! Multiply

3DNow! Convert

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