MC68HC908GR4MP datasheet(27/286 Pages) FREESCALE

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MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

Chapter 2

Memory Map

2.1 Introduction

The CPU08 can address 64K bytes of memory space. The memory map, shown in Figure 2-1, includes:

•

8K bytes of FLASH memory, 7680 bytes of user space on the MC68HC908GR8 or

4K bytes of FLASH memory, 4096 bytes of user space on the MC68HC908GR4

•

384 bytes of random-access memory (RAM)

•

36 bytes of user-defined vectors

•

310 bytes of monitor routines in read-only memory (ROM)

•

544 bytes of integrated FLASH burn-in routines in ROM

2.2 Unimplemented Memory Locations

Accessing an unimplemented location can cause an illegal address reset if illegal address resets are

enabled. In the memory map (Figure 2-1) and in register figures in this document, unimplemented

locations are shaded.

2.3 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and

in register figures in this document, reserved locations are marked with the word Reserved or with the

letter R.

2.4 Input/Output (I/O) Section

Most of the control, status, and data registers are in the zero page area of $0000–$003F. Additional I/O

registers have these addresses:

•

$FE00; SIM break status register, SBSR

•

$FE01; SIM reset status register, SRSR

•

$FE03; SIM break flag control register, SBFCR

•

$FE04; interrupt status register 1, INT1

•

$FE05; interrupt status register 2, INT2

•

$FE06; interrupt status register 3, INT3

•

$FE07; reserved FLASH test control register, FLTCR

•

$FE08; FLASH control register, FLCR

•

$FE09; break address register high, BRKH

•

$FE0A; break address register low, BRKL

•

$FE0B; break status and control register, BRKSCR

•

$FE0C; LVI status register, LVISR

•

$FF7E; FLASH block protect register, FLBPR

Data registers are shown in Figure 2-2, and Table 2-1 is a list of vector locations.

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