MC68HC908GR4MP datasheet(79/286 Pages) FREESCALE

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CGMC Registers

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

7.5 CGMC Registers

These registers control and monitor operation of the CGMC:

•

PLL control register (PCTL)

(See 7.5.1 PLL Control Register.)

•

PLL bandwidth control register (PBWC)

(See 7.5.2 PLL Bandwidth Control Register.)

•

PLL multiplier select register high (PMSH)

(See 7.5.3 PLL Multiplier Select Register High.)

•

PLL multiplier select register low (PMSL)

(See 7.5.4 PLL Multiplier Select Register Low.)

•

PLL VCO range select register (PMRS)

(See 7.5.5 PLL VCO Range Select Register.)

•

PLL reference divider select register (PMDS)

(See 7.5.6 PLL Reference Divider Select Register.)

Figure 7-3 is a summary of the CGMC registers.

Addr.

Bit 7

654321

Bit 0

$0036

PLL Control Register

(PCTL)

Read:

PLLIE

PLLF

PLLON

BCS

PRE1

PRE0

VPR1

VPR0

Write:

Reset:

00100000

$0037

PLL Bandwidth Control

Read:

AUTO

LOCK

ACQ

0000

Write:

Reset:

00000000

$0038

PLL Multiplier Select High

Read:

0000

MUL11

MUL10

MUL9

MUL8

Write:

Reset:

00000000

$0039

PLL Multiplier Select Low

Read:

MUL7

MUL6

MUL5

MUL4

MUL3

MUL2

MUL1

MUL0

Write:

Reset:

01000000

$003A

PLL VCO Select Range

Read:

VRS7

VRS6

VRS5

VRS4

VRS3

VRS2

VRS1

VRS0

Write:

Reset:

01000000

$003B

PLL Reference Divider

Select Register (PMDS)

Read:

0000

RDS3

RDS2

RDS1

RDS0

Write:

Reset:

00000001

= Unimplemented

= Reserved

NOTES:

1. When AUTO = 0, PLLIE is forced clear and is read-only.

2. When AUTO = 0, PLLF and LOCK read as clear.

3. When AUTO = 1, ACQ is read-only.

4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.

5. When PLLON = 1, the PLL programming register is read-only.

6. When BCS = 1, PLLON is forced set and is read-only.

Figure 7-3. CGMC I/O Register Summary

MC68HC908GR4MP Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

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