MC68HC908GR4MP datasheet(64/286 Pages) FREESCALE

64 / 286 page

Break Module (BRK)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

Figure 6-1. Break Module Block Diagram

6.3.2 CPU During Break Interrupts

The CPU starts a break interrupt by:

•

Loading the instruction register with the SWI instruction

•

Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)

The break interrupt begins after completion of the CPU instruction in progress. If the break address

Addr.

Bit 7

654321

Bit 0

$FE00

SIM Break Status Register

(SBSR)

Read:

000100

Write:

RRRRRR

NOTE

Reset:

00010000

$FE03

SIM Break Flag Control

Read:

BCFE

RRRRRRR

Write:

Reset:

$FE09

Break Address Register High

(BRKH)

Read:

Bit 15

Bit 8

Write:

Reset:

00000000

$FE0A

Break Address Register Low

(BRKL)

Read:

Bit 7

654321

Bit 0

Write:

Reset:

00000000

$FE0B

Break Status and Control

Read:

BRKE

BRKA

000000

Write:

Reset:

00000000

Note: Writing a logic 0 clears BW.

= Unimplemented

= Reserved

Figure 6-2. I/O Register Summary

IAB15–IAB8

IAB7–IAB0

8-BIT COMPARATOR

CONTROL

BREAK ADDRESS REGISTER LOW

BREAK ADDRESS REGISTER HIGH

IAB15–IAB0

BREAK

MC68HC908GR4MP Datasheet(PDF) 64 Page - Freescale Semiconductor, Inc

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