MC68HC908GR4MP datasheet(65/286 Pages) FREESCALE

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Low-Power Modes

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

6.3.3 TIMI and TIM2 During Break Interrupts

A break interrupt stops the timer counters and inhibits input captures.

6.3.4 COP During Break Interrupts

The COP is disabled during a break interrupt when VTST is present on the RST pin.

6.4 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.

6.4.1 Wait Mode

If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from

the return address on the stack if SBSW is set. See Chapter 3 Low-Power Modes. Clear the BW bit by

writing logic 0 to it.

6.4.2 Stop Mode

A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register.

6.5 Break Module Registers

These registers control and monitor operation of the break module:

•

Break status and control register (BRKSCR)

•

Break address register high (BRKH)

•

Break address register low (BRKL)

•

SIM break status register (SBSR)

•

SIM break flag control register (SBFCR)

6.5.1 Break Status and Control Register

The break status and control register (BRKSCR) contains break module enable and status bits.

BRKE — Break Enable Bit

This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0

to bit 7. Reset clears the BRKE bit.

1 = Breaks enabled on 16-bit address match

0 = Breaks disabled on 16-bit address match

Address:

$FE0E

Bit 7

654321

Bit 0

Read:

BRKE

BRKA

000000

Write:

Reset:

00000000

= Unimplemented

Figure 6-3. Break Status and Control Register (BRKSCR)

MC68HC908GR4MP Datasheet(PDF) 65 Page - Freescale Semiconductor, Inc

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