MC68HC908GR4MP datasheet(66/286 Pages) FREESCALE

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Break Module (BRK)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

BRKA — Break Active Bit

This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to

BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine.

Reset clears the BRKA bit.

1 = (When read) Break address match

0 = (When read) No break address match

6.5.2 Break Address Registers

The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint

address. Reset clears the break address registers.

6.5.3 Break Status Register

The break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode.

The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt.

BW — Break Wait Bit

This read/write bit is set when a break interrupt causes an exit from wait mode. Clear BW by writing a

logic 0 to it. Reset clears BW.

1 = Break interrupt during wait mode

0 = No break interrupt during wait mode

BW can be read within the break interrupt routine. The user can modify the return address on the stack

by subtracting 1 from it.

Address:

$FE09

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

00000000

Figure 6-4. Break Address Register High (BRKH)

Address:

$FE0A

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

00000000

Figure 6-5. Break Address Register Low (BRKL)

Address:

$FE00

Bit 7

654321

Bit 0

Read:

000100

Write:

RRRRRR

NOTE

Reset:

00010000

Note: Writing a logic 0 clears BW.

= Reserved

Figure 6-6. SIM Break Status Register (SBSR)

MC68HC908GR4MP Datasheet(PDF) 66 Page - Freescale Semiconductor, Inc

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