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MC68HC908GR4MP Datasheet(PDF) 69 Page - Freescale Semiconductor, Inc

Part # MC68HC908GR4MP
Description  M68HC08 Microcontrollers
PDF  286 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC68HC908GR4MP Datasheet(HTML) 69 Page - Freescale Semiconductor, Inc

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MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Freescale Semiconductor
69
Chapter 7
Clock Generator Module (CGMC)
7.1 Introduction
This section describes the clock generator module. The CGMC generates the crystal clock signal,
CGMXCLK, which operates at the frequency of the crystal. The CGMC also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL)
clock, CGMVCLK, divided by two. In user mode, CGMOUT is the clock from which the SIM derives the
system clocks, including the bus clock, which is at a frequency of CGMOUT/2. In monitor mode, PTC3
determines the bus clock. The PLL is a fully functional frequency generator designed for use with crystals
or ceramic resonators. The PLL can generate an 8-MHz bus frequency using a 32-kHz crystal.
7.2 Features
Features of the CGMC include:
•
Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal
reference
•
Low-frequency crystal operation with low-power operation and high-output frequency resolution
•
Programmable prescaler for power-of-two increases in frequency
•
Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
•
Automatic bandwidth control mode for low-jitter operation
•
Automatic frequency lock detector
•
CPU interrupt on entry or exit from locked condition
•
Configuration register bit to allow oscillator operation during stop mode
7.3 Functional Description
The CGMC consists of three major submodules:
•
Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency
clock, CGMXCLK.
•
Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock,
CGMVCLK.
•
Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives
the system clocks from either CGMOUT or CGMXCLK.
Figure 7-1 shows the structure of the CGMC.



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