MC68HC908GR4MP datasheet(72/286 Pages) FREESCALE

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Clock Generator Module (CGMC)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,

CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The

loop filter then slightly alters the DC voltage on the external capacitor connected to CGM/XFC based on

the width and direction of the correction pulse. The filter can make fast or slow corrections depending on

its mode, described in 7.3.4 Acquisition and Tracking Modes. The value of the external capacitor and the

reference frequency determine the speed of the corrections and the stability of the PLL.

The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final

reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final

reference frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on

this comparison.

7.3.4 Acquisition and Tracking Modes

The PLL filter is manually or automatically configurable into one of two operating modes:

•

Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the

VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the

VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in

the PLL bandwidth control register. (See 7.5.2 PLL Bandwidth Control Register.)

•

Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the

VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL

enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected

as the base clock source. (See 7.3.8 Base Clock Selector Circuit.) The PLL is automatically in

tracking mode when not in acquisition mode or when the ACQ bit is set.

7.3.5 Manual and Automatic PLL Bandwidth Modes

The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.

Automatic mode is recommended for most users.

In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between

acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the

VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 7.5.2 PLL

Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt

request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit

continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set,

the VCO clock is safe to use as the source for the base clock. (See 7.3.8 Base Clock Selector Circuit.) If

the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a

severe noise hit and the software must take appropriate action, depending on the application. (See

Interrupts for information and precautions on using interrupts.)

The following conditions apply when the PLL is in automatic bandwidth control mode:

•The ACQ bit (see 7.5.2 PLL Bandwidth Control Register) is a read-only indicator of the mode of the

filter. (See 7.3.4 Acquisition and Tracking Modes.)

•The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the

VCO frequency is out of a certain tolerance. (See 7.8 Acquisition/Lock Time Specifications for

more information.)

•

The LOCK bit is a read-only indicator of the locked state of the PLL.

MC68HC908GR4MP Datasheet(PDF) 72 Page - Freescale Semiconductor, Inc

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