MC68HC908GR4MP datasheet(57/286 Pages) FREESCALE

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Interrupts

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

[CGMOUT]), this 16-

μs conversion can take up to 17 μs to complete. This worst-case could occur if the

write to the ADSCR happened directly after the rising edge of the ADC internal clock causing the

conversion to wait until the next rising edge of the ADC internal clock. With a 1-MHz ADC internal clock,

the maximum sample rate is 59 kHz to 62 kHz. Refer to 23.12 ADC Characteristics.

5.3.4 Conversion

In continuous conversion mode, the ADC data register will be filled with new data after each conversion.

Data from the previous conversion will be overwritten whether that data has been read or not.

Conversions will continue until the ADCO bit is cleared. The COCO bit is set after the first conversion and

will stay set until the next write of the ADC status and control register or the next read of the ADC data

In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs

between writes to the ADSCR.

5.3.5 Accuracy and Precision

The conversion process is monotonic and has no missing codes. See Chapter 23 Electrical Specifications

for accuracy information.

5.4 Interrupts

When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC

conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a

conversion complete flag when interrupts are enabled.

5.5 Low-Power Modes

The WAIT and STOP instruction can put the MCU in low power-consumption standby modes.

5.5.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC

can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power

down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the

WAIT instruction.

5.5.2 Stop Mode

The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.

ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the

analog circuitry before attempting a new ADC conversion after exiting stop mode.

16 to 17 ADC Clock Cycles

Conversion Time =

⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯

ADC Clock Frequency

Number of Bus Cycles = Conversion Time x Bus Frequency

MC68HC908GR4MP Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc