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MC68HC908GR4MP Datasheet(PDF) 56 Page - Freescale Semiconductor, Inc |
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MC68HC908GR4MP Datasheet(HTML) 56 Page - Freescale Semiconductor, Inc |
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56 / 286 page ![]() Analog-to-Digital Converter (ADC) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 56 Freescale Semiconductor Figure 5-1. ADC Block Diagram 5.3.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $FF (full scale). If the input voltage equals VREFL, the ADC converts it to $00. Input voltages between VREFH and VREFL are a straight-line linear conversion. All other input voltages will result in $FF, if greater than VREFH. NOTE Inside the ADC module, the reference voltage, VREFH is connected to the ADC analog power VDDAD; and VREFL is connected to the ADC analog ground VDDAD. Therefore, the ADC input voltage should not exceed the analog supply voltages For operation, VDDAD should be tied to the same potential as VDD via separate traces 5.3.3 Conversion Time Sixteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on the first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC internal clock is selected to run at 1 MHz, then one conversion will take 16 μs to complete. But since the ADC can run almost completely asynchronously to the bus clock, (for example, the ADC is configured to derive its internal clock from CGMXCLK and the bus clock is being derived from the PLL within the CGM INTERNAL DATA BUS READ DDRBx WRITE DDRBx RESET WRITE PTBx READ PTBx PTBx DDRBx PTBx INTERRUPT LOGIC CHANNEL SELECT CLOCK GENERATOR CONVERSION COMPLETE ADC (VADIN) ADC CLOCK CGMXCLK BUS CLOCK ADCH4–ADCH0 ADC DATA REGISTER AIEN COCO DISABLE DISABLE ADC CHANNEL x ADIV2–ADIV0 ADICLK VOLTAGE IN ADC |
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