MC68HC908GR4MP datasheet(46/286 Pages) FREESCALE

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Resets and Interrupts

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

POR — Power-On Reset Flag

1 = Power-on reset since last read of SRSR

0 = Read of SRSR since last power-on reset

PIN — External Reset Flag

1 = External reset via RST pin since last read of SRSR

0 = POR or read of SRSR since last external reset

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by timeout of COP counter

0 = POR or read of SRSR

ILOP — Illegal Opcode Reset Bit

1 = Last reset caused by an illegal opcode

0 = POR or read of SRSR

ILAD — Illegal Address Reset Bit

1 = Last reset caused by an opcode fetch from an illegal address

0 = POR or read of SRSR

MODRST — Monitor Mode Entry Module Reset Bit

1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after

POR while IRQ = VDD

0 = POR or read of SRSR

LVI — Low-Voltage Inhibit Reset Bit

1 = Last reset caused by low-power supply voltage

0 = POR or read of SRSR

4.3 Interrupts

An interrupt temporarily changes the sequence of program execution to respond to a particular event. An

interrupt does not stop the operation of the instruction being executed, but begins when the current

instruction completes its operation.

Address:

$FE01

Bit 7

654321

Bit 0

Read:

POR

COP

ILOP

ILAD

MODRST

LVI

Write:

POR:

10000000

= Unimplemented

Figure 4-2. SIM Reset Status Register (SRSR)

MC68HC908GR4MP Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc

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