 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MC68HC908GR4MP Datasheet(PDF) 134 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MC68HC908GR4MP Datasheet(HTML) 134 Page - Freescale Semiconductor, Inc |
|
|
134 / 286 page  Monitor ROM (MON) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 134 Freescale Semiconductor Figure 15-2 shows a simplified diagram of the monitor mode entry when the reset vector is blank and just 1 x VDD voltage is applied to the IRQ pin. An external oscillator of 9.8304 MHz is required for a baud rate of 9600, as the internal bus frequency is automatically set to the external frequency divided by four. Enter monitor mode with pin configuration shown in Figure 15-1 by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is ready to receive a command. NOTE The PTA1 pin must remain at logic 0 for 24 bus cycles after the RST pin goes high to enter monitor mode properly. Table 15-1. Monitor Mode Signal Requirements and Options IRQ RESET $FFFE/ $FFFF PLL PTB0 PTB1 External Clock(1) 1. External clock is derived by a 32.768 kHz crystal or a 9.8304 MHz off-chip oscillator CGMOUT Bus Freq COP For Serial Communication Comment PTA0 PTA1 Baud Rate(2) (3) 2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication 3. PTA1 = 0 → serial, PTA1 = 1 → parallel communication for security code entry 4. DNA = does not apply, X = don’t care XGND X X X X X 0 0 Disabled X X 0 No operation until reset goes high VTST VDD or VTST XOFF 1 0 9.8304 MHz 4.9152 MHz 2.4576 MHz Disabled 1 0 9600 PTB0 and PTB1 voltages only required if IRQ =VTST X1 DNA VDD VDD $FFFF OFF X X 9.8304 MHz 4.9152 MHz 2.4576 MHz Disabled 1 0 9600 External frequency always divided by 4 X1 DNA GND VDD $FFFF ON X X 32.768 kHz 4.9152 MHz 2.4576 MHz Disabled 1 0 9600 PLL enabled (BCS set) in monitor code X1 DNA VDD or GND VTST $FFFF OFF X X X — — Enabled X X — Enters user mode — will encounter an illegal address reset VDD or GND VDD or VTST Not $FFFF OFF X X X — — Enabled X X — Enters user mode |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
