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STM8L052R8 Datasheet(PDF) 51 Page - STMicroelectronics |
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STM8L052R8 Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 109 page  STM8L052R8 Interrupt vector mapping Doc ID023337 Rev 2 51/109 21 TIM3/USART3 TIM3 update/overflow/ trigger/break USART3 transmission complete/transmit data register empty interrupt -- Yes Yes(5) 0x00 805C 22 TIM3/USART3 TIM3 capture/compareUSART3 Receive register data full/overrun/idle line detected/parity error/ interrupt -- Yes Yes(5) 0x00 8060 23 TIM1 Update /overflow/trigger/ COM -- - Yes(5) 0x00 8064 24 TIM1 Capture/compare - - - Yes(5) 0x00 8068 25 TIM4 TIM4 update/overflow/ trigger -- Yes Yes(5) 0x00 806C 26 SPI1 End of Transfer Yes Yes Yes Yes(5) 0x00 8070 27 USART1/TIM5 USART1 transmission complete/transmit data register empty/ TIM5 update/overflow/ trigger/break -- Yes Yes(5) 0x00 8074 28 USART1/TIM5 USART1 received data ready/overrun error/ idle line detected/parity error/TIM5 capture/compare -- Yes Yes(5) 0x00 8078 29 I2C1/SPI2 I2C1 interrupt(4)/SPI2 Yes Yes Yes Yes(5) 0x00 807C 1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. 2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts. 3. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031). 4. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. 5. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing. Table 9. Interrupt mapping (continued) IRQ No. Source block Description Wakeup from Halt mode Wakeup from Active- halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode)(1) Vector address |
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