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STM8L052R8 Datasheet(PDF) 36 Page - STMicroelectronics |
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STM8L052R8 Datasheet(HTML) 36 Page - STMicroelectronics |
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36 / 109 page  Memory and register map STM8L052R8 36/109 Doc ID023337 Rev 2 0x00 50C0 CLK CLK_CKDIVR Clock master divider register 0x03 0x00 50C1 CLK_CRTCR Clock RTC register 0x00(1) 0x00 50C2 CLK_ICKR Internal clock control register 0x11 0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00 0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x00 0x00 50C5 CLK_CCOR Configurable clock control register 0x00 0x00 50C6 CLK_ECKR External clock control register 0x00 0x00 50C7 CLK_SCSR System clock status register 0x01 0x00 50C8 CLK_SWR System clock switch register 0x01 0x00 50C9 CLK_SWCR Clock switch control register 0xX0 0x00 50CA CLK_CSSR Clock security system register 0x00 0x00 50CB CLK_CBEEPR Clock BEEP register 0x00 0x00 50CC CLK_HSICALR HSI calibration register 0xXX 0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00 0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11100x 0x00 50D0 CLK_PCKENR3 Peripheral clock gating register 3 0x00 0x00 50D1 to 0x00 50D2 Reserved area (2 bytes) 0x00 50D3 WWDG WWDG_CR WWDG control register 0x7F 0x00 50D4 WWDG_WR WWDR window register 0x7F 0x00 50D5 to 00 50DF Reserved area (11 bytes) 0x00 50E0 IWDG IWDG_KR IWDG key register 0xXX 0x00 50E1 IWDG_PR IWDG prescaler register 0x00 0x00 50E2 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 BEEP BEEP_CSR1 BEEP control/status register 1 0x00 0x00 50F1 0x00 50F2 Reserved area (2 bytes) 0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F 0x00 50F4 to 0x00 513F Reserved area (76 bytes) Table 7. General hardware register map (continued) Address Block Register label Register name Reset status |
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