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STM8L052R8 Datasheet(PDF) 74 Page - STMicroelectronics |
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STM8L052R8 Datasheet(HTML) 74 Page - STMicroelectronics |
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74 / 109 page ![]() Electrical parameters STM8L052R8 74/109 Doc ID023337 Rev 2 8.3.4 Clock and timing characteristics HSE external clock (HSEBYP = 1 in CLK_ECKCR) Subject to general operating conditions for VDD and TA. Table 25. Current consumption under external reset Symbol Parameter Conditions Typ. Unit IDD(RST) Supply current under external reset (1) PB1/PB3/PA5 pins are externally tied to VDD VDD = 1.8 V 48 µA VDD = 3 V 80 VDD = 3.6 V 95 1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset. PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger. Table 26. HSE external clock characteristics Symbol Parameter Conditions Min. Typ. Max. Unit fHSE_ext (1) 1. Guaranteed by design, not tested in production. External clock source frequency 116 MHz VHSEH OSC_IN input pin high level voltage 0.7 x VDD VDD V VHSEL OSC_IN input pin low level voltage VSS 0.3 x VDD Cin(HSE) (1) OSC_IN input capacitance 2.6 pF ILEAK_HSE OSC_IN input leakage current VSS < VIN < VDD ±1 µA |
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