MFS2401AVMAFES datasheet(20/151 Pages) NXP

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NXP Semiconductors

FS2400

Fail-safe system basis chip with SMPS and LDO, CAN FD transceiver

7.5.1 Electrical characteristics

TA = –40 °C to 115 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages referenced

to ground.

Symbol

Parameter

Min

Typ

Max

Unit

Debug mode

VDBG_MODE

Voltage to apply at DBG pin to enter Debug mode

3.5

4.5

5.5

TDBG_MODE

Debug mode entry filtering time

5.5

VOTP_MODE

Voltage to apply at DBG pin to program the OTP

7.75

7.95

8.15

TOTP_MODE

OTP mode entry filtering time

5.5

IDBG

DBG pin input current consumption

µA

Table 5. Electrical characteristics

7.6 MCU programming

MCU programming can be done at any time. To prevent any watchdog error detection and RSTB pin assertion

while programming, the watchdog period should be extended (up to 16384 ms) or set as infinite (window is fully

opened). If the watchdog is not disabled, the user must refresh it during the MCU programming.

To disable the watchdog, NXP advises the user to start the device in Debug mode by applying the correct

voltage to the DEBUG pin before M4 state.

7.7 Best of supply (BOS)

7.7.1 Functional description

The VBOS regulator manages the best of supply from VSUP or V1 to efficiently generate the internal biasing of

the device, in all device modes. VBOS is also the supply of V1 High-Side and Low-Side gate drivers.

VBOS undervoltage may not guarantee the full functionality of the device. Consequently, VBOS_UV detection

powers down the device by going into fail-safe state.

VBOS is composed of two regulators implemented in parallel: VBOS_HP used to supply the HP analog internal

biasing, and VBOS_LP used to supply the internal biasing in Low-power modes.

At power up, VBOS_LP is automatically enabled. VBOS_HP is enabled when the HP analog circuitry is enabled

(State #M2). Both VBOS_LP and VBOS_HP are generated from VSUP.

In LPON mode, VBOS can be connected to V1 (VBOS2V1 switch closed) to optimize the efficiency. This way,

the current consumption beneficiate from the VBAT to V1 ratio and is reduced. This function is enabled or

disabled by OTP using VBOS2V1_SW_LP_EN_OTP bit.

When waking up from LPON mode, VBOS transition to VBOS_LP than immediately to VBOS_HP.

In LPOFF mode, only VBOS_LP is enabled.

The behavior of the VBOS regulator is summarized in Figure 15.

FS2400

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 23 October 2024

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