SNLS059E datasheet(32/110 Pages) TI2

32 / 110 page

3.0 Functional Description (Continued)

Subject to change without notice.

Rev O www.national.com

The receive interface consists of a nibble wide data bus

RXD[3:0], a receive error signal RXER, a receive data valid

flag RXDV, and a receive clock RXCLK for synchronous

transfer of the data. The receive clock can operate at 2.5

MHz to support 10 Mb/s operation modes or at 25 MHz to

support 100 Mb/s operational modes.

The transmit interface consists of a nibble wide data bus

TXD[3:0], a transmit enable control signal TXEN, and a

transmit clock TXCLK which runs at 2.5 MHz or 25 MHz.

Additionally, the MII includes the carrier sense signal CRS,

as well as a collision detect signal COL. The CRS signal

asserts to indicate the reception of data from the network

or as a function of transmit data in Half Duplex mode. The

COL signal asserts as an indication of a collision which can

occur during half-duplex operation when both a transmit

and receive operation occur simultaneously.

3.12.6 Collision Detection

For Half Duplex, a 10BASE-T or 100BASE-TX collision is

detected when the receive and transmit channels are

active simultaneously. Collisions are reported by the COL

signal on the MII.

If the PHY is transmitting in 10 Mb/s mode when a collision

is detected, the collision is not reported until seven bits

have been received while in the collision state. This

prevents a collision being reported incorrectly due to noise

on the network. The COL signal remains set for the

duration of the collision.

If a collision occurs during a receive operation, it is

immediately reported by the COL signal.

When heartbeat is enabled (only applicable to 10 Mb/s

operation), approximately 1

µs after the transmission of

each packet, a Signal Quality Error (SQE) signal of

approximately 10 bit times is generated (internally) to

indicate successful transmission. SQE is reported as a

pulse on the COL signal of the MII.

3.12.7 Carrier Sense

Carrier Sense (CRS) is asserted due to receive activity,

once valid data is detected, during 10 Mb/s operation.

During 100 Mb/s operation CRS is asserted when a valid

link (SD) and two non-contiguous zeros are detected.

For 10 or 100 Mb/s Half Duplex operation, CRS is asserted

during either packet transmission or reception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted

only due to receive activity.

CRS is de-asserted following an end of packet.

Figure 3-16 Typical MDC/MDIO Write Operation

MDC

MDIO

11 0 0 00 0 0 0

(STA)

Idle

Start Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

0 0 0

0 00

00 0 0 0 00 0 Z

Idle

10 0

SNLS059E Datasheet(PDF) 32 Page - Texas Instruments

SNLS059E Datasheet(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL