SNLS059E datasheet(57/110 Pages) TI2

57 / 110 page

4.0 Register Set (Continued)

Subject to change without notice.

Rev O www.national.com

4.2.14.1 Wake on LAN

The Wake on LAN logic provides several mechanisms for

bringing the DP83815 out of a low-power state. Wake on

ARP, Wake on Broadcast, Wake on Multicast Hash and

Wake on Phy Interrupt are enabled by setting the

corresponding bit in the Wake Command/Status Register,

WCSR. Before the hardware is programmed to a low

power state, the software must write a null receive

descriptor pointer to the Receive Descriptor Pointer

the RX fifo. Please refer to the description of the RXDP

When a qualifying packet is received, the Wake on LAN

logic generates a Wake event and pulses the PMEN PCI

signal to request a Power Management state change. The

software must then bring the hardware out of low power

mode and, if the Power Management state was D3hot,

reinitialize Configuration Register space. A Wake interrupt

can also be generated which alerts the software that a

Wake event has occurred and a packet was received. The

software must then write a valid receive descriptor pointer

to RXDP. The incoming packet can then be transferred into

host memory for processing. Note that the wake packet is

retained for processing - this is a feature of the DP83815.

In addition to the above Wake on LAN features, DP83815

also provides Wake on Pattern Matching, Wake on DA

match and Wake on Magic Packet.

Wake on Pattern Matching

Wake on Pattern Matching is an extension of the Pattern

Matching feature provided by the Receive Filter Logic.

When one or more of the Wake on Pattern Match bits are

set in the WCSR, a packet will generate a wake event if it

matches the associated pattern buffer. The pattern count

and the pattern buffer memory are accessed in the same

way as in Pattern Matching for packet acceptance. The

minimum pattern count is 2 bytes and the maximum pattern

count is 64 bytes for patterns 0 and 1, and 128 bytes for

patterns 2 and 3. Packets are compared on a byte by byte

basis and bytes may be masked in pattern memory, thus

allowing for don’t cares. Refer to Section 4.2.18 Receive

Filter Logic for programming examples.

Bit

Bit Name

Description

WKPAT0

Wake on Pattern 0 match

Enable wake on match of pattern 0. R/W

WKARP

Wake on ARP

Enable wake on ARP packet detection. R/W

WKBCP

Wake on Broadcast

Enable wake on broadcast packet detection. R/W

WKMCP

Wake on Multicast

Enable wake on multicast packet detection. R/W

WKUCP

Wake on Unicast

Enable wake on unicast packet detection. R/W

WKPHY

Wake on Phy Interrupt

Enable wake on Phy Interrupt. The Phy interrupt can be programmed for Link Change and a variety of

other Physical Layer events. R/W

SNLS059E Datasheet(PDF) 57 Page - Texas Instruments

SNLS059E Datasheet(HTML) 57 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL