SNLS059E datasheet(84/110 Pages) TI2

84 / 110 page

5.0 Buffer Management (Continued)

Subject to change without notice.

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5.2 Transmit Architecture

The following figure illustrates the transmit architecture of the DP83815 10/100 Ethernet Controller.

Figure 5-4 Transmit Architecture

When the CR:TXE bit is set to 1 (regardless of the current state), and the DP83815 transmitter is idle, then DP83815 will

read the contents of the current transmit descriptor into the TxDescCache. The DP83815’s TxDescCache can hold a

single fragment pointer/count combination.

5.2.1 Transmit State Machine

The transmit state machine has the following states:

The transmit state machine manipulates the following internal data spaces:

Inputs to the transmit state machine include the following events:

Transmit Descriptor

Current Tx Desc Ptr

Software/Memory

Hardware

Tx Data FIFO

link

cmdsts

ptr

Tx DMA

cmdsts

Packet

TxHead

link

Tx Desc Cache

txIdle

The transmit state machine is idle.

txDescRefr

Waiting for the "refresh" transfer of the link field of a completed descriptor from the PCI bus.

txDescRead

Waiting for the transfer of a complete descriptor from the PCI bus into the

TxDescriptorCache.

txFifoBlock

Waiting for free space in the TxDataFIFO to reach TxFillThreshold.

txFragRead

Waiting for the transfer of a fragment (or portion of a fragment) from the PCI bus to the

TxDataFIFO.

txDescWrite

Waiting for the completion of the write of the cmdsts field of an intermediate transmit

descriptor (cmdsts.MORE == 1) to host memory.

txAdvance

(transitory state) Examine the link field of the current descriptor and advance to the next

descriptor if link is not NULL.

TXDP

A 32-bit register that points to the current transmit descriptor.

CTDD

An internal bit flag that is set when the current transmit descriptor has been completed, and

ownership has been returned to the driver. It is cleared whenever TXDP is loaded with a

new value (either by the state machine, or the driver).

TxDescCache

An internal data space equal to the size of the maximum transmit descriptor supported.

descCnt

Count of bytes remaining in the current descriptor.

fragPtr

Pointer to the next unread byte in the current fragment.

txFifoCnt

Current amount of data in the txDataFifo in bytes.

txFifoAvail

Current amount of free space in the txDataFifo in bytes (size of the txDataFifo - txFifoCnt).

CR:TXE

Driver asserts the TXE bit in the command register (similar to SONIC).

XferDone

Completion of a PCI bus transfer request.

FifoAvail

TxFifoAvail is greater than TxFillThreshold.

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