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4.0 Register Set (Continued)

4.2.11 Receive Descriptor Pointer Register

This register points to the current Receive Descriptor.

Bit

Bit Name

Description

22-20

MXDMA

Max DMA Burst Size per Tx DMA Burst

This field sets the maximum size of transmit DMA data bursts according to the following table:

000 = 128 32-bit words (512 bytes)

001 = 1 32-bit word (4 bytes)

010 = 2 32-bit words (8 bytes)

011 = 4 32-bit words (16 bytes)

100 = 8 32-bit words (32 bytes)

101 = 16 32-bit words (64 bytes)

110 = 32 32-bit words (128 bytes)

111 = 64 32-bit words (256 bytes)

NOTE: The MXDMA setting value MUST not be greater than the TXCFG:FLTH (Tx Fill Threshold) value.

19-14

unused

13-8

FLTH

Tx Fill Threshold

Specifies the fill threshold in units of 32 bytes. When the number of available bytes in the transmit FIFO

reaches this level, the transmit bus master state machine will be allowed to request the PCI bus for

transmit packet fragment reads. A value of 0 in this field will produce unexpected results and must not be

used.

Note: The FLTH value should be greater than the TXCFG:MXDMA value, but less than (txFIFOsize -

TXCFG:DRTH). In order to prevent FIFO pointer overlap internal to the device, the sum of the FLTH and

TXCFG:DRTH values should not exceed 2016 Bytes.

7-6

unused

5-0

DRTH

Tx Drain Threshold

Specifies the drain threshold in units of 32 bytes. When the number of bytes in the FIFO reaches this

level (or the FIFO contains at least one complete packet) the MAC transmit state machine will begin the

transmission of a packet.

NOTE: In order to prevent a deadlock condition from occurring, the DRTH value should always be less

than (txFIFOsize - TXCFG:FLTH). A value of 0 in this field will produce unexpected results and must not

be used. Also, in order to prevent FIFO pointer overlap internal to the device, the sum of the DRTH and

TXCFG:FLTH values should not exceed 2016 Bytes.

Tag: RXDP

Size: 32 bits

Hard Reset: 00000000h

Offset: 0030h

Access: Read Write

Soft Reset: 00000000h

Bit

Bit Name

Description

31-2

RXDP

Receive Descriptor Pointer

The current value of the receive descriptor pointer. When the receive state machine is idle, software must

set RXDP to the address of an available receive descriptor. While the receive state machine is active,

RXDP will follow the state machine as it advances through a linked list of available descriptors. If the link

field of the current receive descriptor is NULL (signifying the end of the list), RXDP will not advance, but

will remain on the current descriptor. Any subsequent writes to the RXE bit of the CR register will cause

the receive state machine to reread the link field of the current descriptor to check for new descriptors

that may have been appended to the end of the list. Software should not write to this register unless the

receive state machine is idle. Receive descriptors must be aligned on 32-bit boundaries (A1-A0 must be

zero). A 0 written to RXDP followed by a subsequent write to RXE will cause the receiver to enter silent

RX mode, for use during WOL. In this mode packets will be received and buffered in FIFO, but no DMA

to system memory will occur. The packet data may be recovered from the FIFO by writing a valid

descriptor address to RXDP and then strobing RXE.

1-0

unused

SNLS059E Datasheet(PDF) 52 Page - Texas Instruments

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