LM4931ITLSLASHNOPB datasheet(16/50 Pages) TI2

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LM4931

SNAS251E – APRIL 2004 – REVISED MAY 2013

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Table 11. LS_GAIN (04h) (SET = LOGIC 1, CLEAR = LOGIC 0)

Address

Description

4:0

LS_GAIN

Programs the gain of the loudspeaker amplifier. Gain is set as follows:

4:0

Loudspeaker Gain

4:0

Loudspeaker Gain

00000

–34.5dB

10000

–10.5dB

00001

–33dB

10001

–9dB

00010

–31.5dB

10010

–7.5dB

00011

–30dB

10011

–6dB

00100

–28.5dB

10100

–4.5dB

00101

–27dB

10101

–3dB

00110

–25.5dB

10110

–1.5dB

00111

–24dB

10111

0dB

01000

–22.5dB

11000

1.5dB

01001

–21dB

11001

3dB

01010

–19.5dB

11010

4.5dB

01011

–18dB

11011

6dB

01100

–16.5dB

11100

7.5dB

01101

–15dB

11101

9dB

01110

–13.5dB

11110

10.5dB

01111

–12dB

11111

12dB

LS_MUTE

If set the loudspeaker amplifier is muted.

LS_AUTO_MUTE

If set the loudspeaker amplifier is automatically muted when the headphone sense detects that the

headphones have been connected. This uses the conditions set by HP_SENSE_TYPE to determine

if the headphones are connected.

LS_PWDN

If set the Class D amplifier is disabled. If an external amplifier is being used, an enable signal can

be accessed on the GPIO.

PLL Configuration Registers

This register is used to control the frequency divider (M divider) which sits before the PLL phase comparator, it

also allows the 3 MSBs of the N_divider’s modulus input to be programmed. See Figure 5 for further explanation.

Table 12. DEFAULT CHART FOR PLL_M (05h)

DATA BIT

DEFAULT

Table 13. PLL_M (05h) (SET = LOGIC 1, CLEAR = LOGIC 0)

Address

Description

4:0

PLL_M

Programs the PLL input divider from divide by 4 to divide by 31. It is also possible to

bypass the divider if PLL_M = 1 or divide by 2 if PLL_M = 2. Setting PLL_M = 3 will

default to divide by 4.

7:5

PLL_N_MOD1

Programs the modulus bits [4:2] of the PLL feedback divider .

This register is used to control the integer of the PLL feedback divider (fractional N divider).

Table 14. DEFAULT CHART FOR PLL_N (06h)

DATA BIT

DEFAULT

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