LM4931ITLSLASHNOPB datasheet(39/50 Pages) TI2

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LM4931

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SNAS251E – APRIL 2004 – REVISED MAY 2013

4. The serial data bits are sampled at the rising edge of SCK. Any transition on SDI must occur at least 100ns

(tSPISETHOLDD) before the rising edge of SCK. Also, any transition on SDI must occur at least 100ns (tSPISETD) after

the rising edge of SCK and stabilize before the next rising edge of SCK.

5. ENB should be logic-low only during serial data transmission.

6. ENB must be logic-low at least 100ns (tSPISETENB ) before the first rising edge of SCK, and ENB has to remain

logic-low at least 100ns (tSPIHOLDENB) after the sixteenth rising edge of SCK.

7. If ENB remains logic-high for mtore than 10ns before all 16 bits are transmitted then the data latch will be

aborted.

8. If ENB is logic-low for more than 16 SCK pulses then only the first 16 data bits will be latched and activated

when ENB transitions to logic-high.

9. ENB must remain logic-low for at least 100ns (tSPIHOLDENB ) to latch in the data.

10. Coincidental rising or falling edges of SCK and ENB are not allowed. If SCK is to be held logic-high after the

data transmission, the falling edge of SCK must occur at least 100ns before ENB transitions to logic-low for the

next set of data.

LM4931 Evaluation Software

The LM4931 demoboard can be easily evaluated with the accompanying LM4931 Evaluation Software. The

Windows 95/98/2000/NT/XP compatible software is a GUI that allows easy access to all the I2C/SPI internal

registers of the device. The GUI controls the PC parallel port to deliver the appropriate I2C/SPI commands via

the Texas Instruments I2C/SPI Interface Card, in order to properly program the LM4931.

PCM Bus Interface (JP12)

PCM_SDO, PCM_SYNC, PCM_SDI, and PCM_CLK form the PCM interface bus for simple communication with

most baseband ICs with voiceband communications and follow the PCM-1900 communications standard. The

PCM interface features a frame length of 16 bits, A-law and u-law companded, linear mode, short or long frame

sync, an energy-saving power down mode, and master or slave operation. PCM_SYNC is the word sync line for

the bus. It may be set in the INTERFACES (09h) register (bit 3 PCM_LONG) for short or long frame sync. A

short frame sync is 1 PCM_CLK cycle (PCM_LONG=0), a long frame sync is an inverted version of short sync

(PCM_LONG=1). This is illustrated by Figure 7 in the PCM timing diagram under the Audio Interfaces section.

PCM_CLK is the bit clock for the bus. Its frequency is fixed at 128kHz and may be generated by the LM4931

when the PCM section is set to operate in master mode by setting bit 2 of the INTERFACES (09h) register.

Clearing this same bit (bit 2) places the PCM section into slave mode where an external clock must be provided.

The other two lines, PCM_SDO and PCM_SDI, are for serial data out and serial data in, respectively. The type of

data may also be set in the INTERFACES (09h) register by bits 0 and 1. Bit 0 controls whether the data is linear

or companded. If set to 1, the 8 MSBs are presumed to be companded data and the 8 LSBs are ignored. If

cleared to 0, the data is treated as 2’s complement PCM data. Bit 1 controls which PCM law is used if Bit 0 is set

for companded (G711) data. If set to 1, the companded data is assumed to be A-law. If cleared to 0, the

companded data is treated as µ-law.

I2S Interface Bus (JP13)

The I2S standard provides a uni-directional serial interface designed specifically for digital audio. For the

LM4931, the interface provides access to a 48kHz, 18 bit full-range stereo audio DAC. This interface uses a

three port system of clock (I2S_CLK), data (I2S_SDI), and word (I2S_WS). The clock and word lines can be either

master or slave as set by bit 4 in the INTERFACES (09h) register.

A bit clock (I2S_CLK) at 32 or 64 times the sample frequency is generated by the I2S system master (unless set

as a slave) and a word select (I2S_WS) line is driven at a frequency equal to the sampling rate of the audio data,

up to 48kHz. The word length is set by bit 5 of the INTERFACES (09h) register. When bit 5 is cleared, a word

length of 16 bits is selected. When set, the word length is set to 32 bits. All 18MSBs are passed to the DAC

when the I2S interface is set to 32 bit word mode. In 16 bit mode, all 16 bits are sent to the DAC. The word line is

registered to change on the negative edge of the bit clock. The serial data (I2S_SDI) is sent MSB first, again

registered on the negative edge of the bit clock, delayed by 1 bit clock cycle relative to the changing of the word

line (see Figure 6).

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