LM4931ITLSLASHNOPB datasheet(42/50 Pages) TI2

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LM4931

SNAS251E – APRIL 2004 – REVISED MAY 2013

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The VOICE_CONFIG (01h) register is used to set various configuration parameters on the voiceband and full-

range audio codecs. SIDETONE_ATTEN (bits 3:0) refers to the level of signal from the MIC input that is fed back

into the analog audio output path (commonly used in headphone applications and killed in hands-free

applications). Setting the AUTOSIDE bit (bit 4) automatically mutes the sidetone in voice over mono speaker

modes so feedback isn’t an issue. Dither for the voice ADC and DAC may be disabled by setting bits 6 or 7,

respectively. Bit 5 is reserved.

The MIC_GAIN (02h) register provides for microphone preamplifier gains of 6dB to 36dB in 2dB steps (bits 3:0).

A quick mute bit is provided for the mic (bit 4) as well as a bit to disable the high-pass filter on the voice ADC,

allowing wider bandwidth usage through the microphone input.

The HP_GAIN (03h) register provides settings for headphone control. Bits 4:0 set the gain of the headphone

output from –46.5dB to 0dB in 1.5dB steps. A quick mute bit is also provided (bit 5). Additionally, the LM4931

may be configured to react to a high or low HP_SENSE voltage (bit 6) and may also provide this output on the

GPIO pin in either positive or negative form (bit 7). This will only be seen on the GPIO output if it is configured to

show HP_CONNECTED as described in the GPIO section.

The LS_GAIN (04h) register is used to set the mono class D loudspeaker gain. Bits 4:0 set this from –34.5dB to

+12dB in 1.5dB steps. A quick mute (bit 5) is provided as well as an auto-mute bit (bit 6) that, if set, automatically

mutes the loudspeaker when headphone sense detects that headphones have been connected. A powerdown bit

(bit 7) is also provided to independently shutdown just the class D amplifier.

CLK_MUX (08h) is the clock divider register. Bit 0 sets the PLL input source. When clear, MCLK is used, when

set, the I2S input clock is used. Bit 1 gives a divide by 2 for usage with a faster MCLK (like 24.576MHz). Bit 2

selects which clock is passed to the full range audio subsystem. If clear, the PLL output is used. If set, MCLK (or

MCLK/2 if set) is used directly. Bit 3 does the same for the voice codec subsystem. If clear, the PLL output is

used. If set, MCLK or MCLK/2 is used. Bit 4 powers down the PLL (if not needed). Bits 6:5 program the Q

divider, that can be further used to divide down the PLL output frequency. Bit 7 is reserved.

The INTERFACES (09h) register controls all the digital interface configurations. This may be used to set the

PCM configuration and I2S configuration as stated above in the PCM Bus Interface and I2S Bus Interface

sections. Bits 6 is reserved for test modes.

The PMC_CONFIG (0Ah) register controls various power management responsibilities including bypass

capacitor size (bits 2:1). Zero crossing disable (bit 0) is also provided to allow the LM4931 to change modes

regardless of zero crossing detect status. If set, the LM4931 will change modes immediately without waiting for

the outputs to cross zero. Bits 6 is reserved.

PLL Registers

The PLL will accept incoming clock frequencies from 10MHz to 25MHz. However, since the control clocks, PCM

clocks, and I2S clocks all operate at fixed, defined frequencies the PLL must also be configured to match the

incoming frequency and provide the correct output for all the parts of the subsystem.

The first register, PLL_M (05h), sets the PLL input divider. Bits 4:0 of this register are used to set the divider

from 4 to 31. It is also possible to bypass the divider (M =1) by setting PLL_M to 0001b. Setting PLL_M to 0010b

gives a divide by 2. Setting PLL_M to 0011b gives a default divider of 4 (as does setting to 0100b). Values above

that are identical to their base 10 integer values. Bits 7:5 programs the modulus bits of the PLL feedback divider.

The second PLL register, PLL_N (06h), sets the PLL feedback divider. Bits 6:0 are used to set the PLL feedback

divider from divide by 4 to divide by 127. Values set from 0 to 3 are rounded to 4. This register also may be used

to alter the speed of the VCO. Setting bit 7 (FAST_VCO) tunes the VCO operation for frequencies up to 100MHz.

Normally it is tuned for outputs around 50MHz.

The final PLL register, PLL_P (07h), sets the PLL output divider. Bits 3:0 set this from divide by 4 to divide by 15.

Inputs of 0 to 3 are rounded to 4. It is also recommended that P = 4 to keep the VCO around its nominal

operating frequency (50MHz if PLL_N bit 7 is clear). The divider modulus may be set by bits 5:4. Additionally, the

dither level for the PLL is controlled in this register in bits 7:6.

The Audio Clock Requirements table details how different clock values may be generated for a given input

clock.

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