LM4931ITLSLASHNOPB datasheet(19/50 Pages) TI2

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MCL

I2S_CL

PCM_CL

PCM

Interface

I2S Interface

Stereo

DAC

Voice Codec

PLL

% Q

% 2

LM4931

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SNAS251E – APRIL 2004 – REVISED MAY 2013

Table 20. CLK_MUX (08h) (SET = LOGIC 1, CLEAR = LOGIC 0) (continued)

Address

Description

If set the master clock is divided by two, for example allowing for a 24.576MHz or PCI

clock to be used(1)(2).

FAST_CLOCK

MCLK Frequency

FAST_CLOCK

Normal

Divided by 2

Selects which clock is passed to the audio sub-system(1):

AUDIO_CLK_SEL

Audio Sub-system

Input Source

AUDIO_CLK_SEL

PLL Output

MCLK / MCLK/2

Selects which clock is passed to the voice sub-system(1):

VOICE_CLK_SEL

Audio Sub-system

Input Source

VOICE_CLK_SEL

PLL Output

MCLK / MCLK/2

PLL_DISABLE

Powers down the PLL if it is not required.

Programs the Q divider (divides from the PLL output frequency of 12.288MHz).

6:5

Divide Value

12 (1.024MHz/8kHz)

6:5

Q_DIV

8 (1.536MHz/12kHz)

6 (2.048MHz/16kHz)

4 (3.072MHz/24kHz)

RSVD

RESERVED(3)

(2)

For inputs greater than 50Mhz, the input clock divider FAST_CLOCK should be set.

(3)

Reserved bits should be set to zero when programming the associated register.

The voice codec operates at 128*fs, so it requires a 1.024MHz clock to operate on 8kHz data. The Audio DAC

also operates at 128*fs, i.e. 6.144MHz for 48kHz data, 5.6448MHz for 44.1kHz data etc. It is expected that the

PLL is used to drive the audio system unless a 12.288MHz or 24.576MHz (AC’97) master clock is supplied and

the sample rate is always 48kHz, in which case the PLL can be bypassed to reduce power.

The voice codec is always driven from the divided down clock from the PLL output or a divided down version of

the master clock. When using the voice codec for 8kHz operation, program the PLL as you would for 48kHz

operation and use Q to divide by (2*FSaudio/FSvoice).

The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output

of the PLL and the voice codec either uses a divided by 6 clock or a divided version of the MCLK pin.

MCLK must be less than or equal to 50MHz if the input divider is to be used, otherwise MCLK can be any

frequency up to 25MHz. The comparison frequency after the M divider should be less than 5MHz

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