LM4931ITLSLASHNOPB datasheet(11/50 Pages) TI2

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Start

Condition

Stop

Condition

Data

ACK

SDA

SCL

TI2CSET

TI2CHOLD

TI2CSET

ACK

Data

ACK

6 - 0

7 - 1

R/W

Host

Address

Start

Condition

SDA

SCL

Address

Stop

Condition

ENB

SCK

SDI

TSPISETENB

TSPIHOLDD

TSPISETD

TSPICH

TSPIT

TSPICL

TSPIHOLDENB

Data

ENB

SCK

SDI

LM4931

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SNAS251E – APRIL 2004 – REVISED MAY 2013

System Control

The LM4931 is controlled via either a three wire SPI or a two wire I2C compatible interface, selectable with the

MODE pin When MODE is cleared the device is in I2C mode, when MODE is set the device is in SPI mode. This

interface is used to configure the operating mode, interfaces, data converters, mixers and amplifiers. The

LM4931 is controlled by writing 8 bit data into a series of write-only registers, the device is always a slave for

both type of interfaces.

THREE WIRE, SPI INTERFACE (MODE = 1)

Figure 3.

When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is

clocked in on the rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are

used to select an address within the device, the lower 8 bits (7:0) contain the updated data for this register.

TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0)

Figure 4.

When the part is configured as an I2C device then the LM4931 will respond to one of two addresses, according

to the ADDR input. If ADDR is low then the address portion of the I2C transaction should be set to write to

0010000. When ADDR is high then the address input should be set to write to 1110000. The LM4931 uses the

following 11 registers to store configuration information:

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