LM4931ITLSLASHNOPB datasheet(38/50 Pages) TI2

38 / 50 page

LM4931

SNAS251E – APRIL 2004 – REVISED MAY 2013

www.ti.com

LM4931ITL DEMO BOARD OPERATION

The LM4931ITL demo board is a complete evaluation platform, designed to give easy access to the control pins

of the part and comprises all the necessary external passive components. Besides the separate analog (JP8),

digital (JP7), PLL (JP9) and Loudspeaker (JP10) supply connectors, the board features seven other major input

and control blocks: an SPI/I2C compatible selectable interface bus (JP11) for the control lines, a PCM interface

bus (JP12) for voiceband digital audio, an I2S interface bus (JP13) for full-range digital audio, an analog mic jack

input (JP1) for connection to an external microphone, a high efficiency class D BTL mono output (JP5) for

connection to an external speaker, a stereo headphone output (JP15 or P1), and an external MCLK input (JP3)

for use in place of the crystal on the demoboard.

SPI/I2C Interface Bus (JP11)

This is the main control bus for the LM4931. This interface may either be configured as a two-wire, I2C

compatible interface by setting MODE = 0 (S1 = IN) or a three-wire SPI interface by setting MODE = 1 (S1 =

OUT).

I2C Compatible Mode (MODE = 0)

The two-wire I2C compatible interface consists of an SDA line (data) and SCL line (clock). Each transmission

from the baseband controller to the LM4931 is given MSB first and must follow the timing intervals given in the

Electrical Characteristics section of the datasheet to create the start and stop conditions for a proper

transmission. The start condition is detected if SCL is high on the falling edge of SDA. The stop condition is

detected if SCL is high on the rising edge of SDA. Repeated start signals are handled correctly. Data is then

transmitted as shown in Figure 4 for the Two Wire I2C Compatible Interface. After the start condition has been

achieved the chip address is sent, followed by a set write bit, wait for ack (SDA will be pulled low by LM4931),

data bits 15-8, wait for ACK (SDA will be pulled low by LM4931), data bits 7-0, wait for ACK (SDA will be pulled

low by LM4931) and finally the stop condition is given.

This same sequence follows for any I2C control bus transmission to the LM4931. The chip address is hardwire

selected by the ADDR Select pin (JP11, pin 4) which may be software enabled high or low with the LM4931

demonstration control software. If ADDR is low, then the chip address is set to 0010000b. If ADDR is high, the

address is set to 1110000b. The 11 control registers are shown on page 13 in the System Control Table. Data

is sampled only if the address is in range and the R/W bit is clear. Data for each register is given in the System

Control section of the datasheet.

Pull-up resistors are required to achieve reliable operation. 10k

Ω pull-up resistors on the SDA and SCL lines

achieves best results when used with TI’s parallel-to-serial interface board. Lower value pull-up resistors will

decrease the rise and fall times on the bus which will in turn decrease susceptibility to bus noise that may cause

a false trigger. The cost comes at extra current use. Control bus reliability will thus depend largely on bus noise

and may vary from design to design. Low noise is critical for reliable operation.

SPI Mode (MODE = 1)

The SPI interface consists of three lines: the serial data input pin (SDI), the clock input pin (SCK), and the SPI

enable pin (ENB).The serial data bits are organized into two fields of 8 bit data as shown on Figure 3 in the

Three Wire, SPI Interface timing diagram. The first 8 bits corresponds to the register address given on the

System Control Table on page 13. The second 8 bits contains the data to write to the desired control register.

These fields are transmitted subsequently to form a 16 bit word. For each SPI transfer, ENB is lowered and the

data bits are written to the SDI pin with the most significant bit (MSB) first. All serial data are sampled at the

rising edge of the SCK signal. Once all the data bits have been sampled, ENB transitions from logic-high to logic-

low to complete the SPI sequence. All 16 bits must be received before any data latch can occur. Any excess

CLK and DATA transitions will be ignored after the sixteenth rising clock edge has occurred. For any data

sequence longer than 16 bits, only the first 16 bits will get loaded into the shift register and the rest of the bits will

be disregarded.

SPI Operational Requirements

1. The data bits are transmitted with the MSB first.

2. The maximum clock rate is 4MHz for the SCK pin.

3. SCK must remain logic-high for at least 500ns (tSPICH ) after the rising edge of SCK, and SCK must remain

logic-low for at least 500ns (tSPICL) after the falling edge of SCK.

Submit Documentation Feedback

Product Folder Links: LM4931

LM4931ITL/NOPB Datasheet(PDF) 38 Page - Texas Instruments

LM4931ITL/NOPB Datasheet(HTML) 38 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL