LM5064PMHSLASHNOPB datasheet(16/64 Pages) TI2

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Load

Current

GATE

TIMER

3.9V

1.2V

4.1 mA

pulldown

52 PA

Gate Charge

74 PA

2.4 PA

Fault Timeout

Period

0.3V

Fault

Detection

ILIMIT

tRESTART

LM5064

Latch

Control

VCC

UVLO/EN

OVLO

VEE

VSYS

LM5064

SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013

www.ti.com

Figure 3. Latched Fault Restart Control

The LM5064 provides an automatic restart sequence which consists of the TIMER pin cycling between 3.9V and

1.2V eight times after the Fault Timeout Period, as shown in Figure 4. The period of each cycle is determined by

the 74 µA charging current, and the 2.4 µA discharge current, and the value of the capacitor CT. When the

TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 52 µA current source at the GATE pin turns on

Q1. If the fault condition is still present, the Fault Timeout Period and the restart sequence repeat. The RETRY

pin allows selecting no retries or infinite retries. Finer control of the retry behavior can be achieved through the

DEVICE_SETUP (D9h) register. Retry counts of 0, 1, 2, 4, 8, 16 or infinite may be selected by setting the

appropriate bits in the DEVICE_SETUP (D9h) register.

Figure 4. Restart Sequence

Under-Voltage Lockout (UVLO)

The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is within the operating range

defined by the programmable under-voltage lockout (UVLO) and over-voltage lockout (OVLO) levels. Typically,

the UVLO level at VSYS is set with a resistor divider (R1-R3) as shown in Figure 5. Referring to the Block

Diagram when VSYS is below the UVLO level, the internal 20 µA current source at UVLO/EN is enabled, the

current source at OVLO is off, and Q1 is held off by the 4.1 mA pull-down current at the GATE pin. As VSYS is

increased, raising the voltage at UVLO/EN above its threshold with respect to VEE, the 20 µA current source at

UVLO/EN is switched off, increasing the voltage at UVLO/EN, providing hysteresis for this threshold. With the

UVLO/EN pin above its threshold, Q1 is switched on by the 52 µA current source at the GATE pin if the insertion

time delay has expired.

See the Application Information section for a procedure to calculate the values of the threshold setting resistors

(R1-R3). The minimum possible UVLO level at VSYS can be set by connecting the UVLO/EN pin to VCC. In this

case Q1 is enabled after the insertion time when the operating voltage (VCC-VEE) reaches the POR threshold.

After power up an UVLO condition will cause the INPUT bit in the STATUS_WORD (79h) register, the

VIN_UV_FAULT bit in the STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the

DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin will be pulled low unless this feature is

disabled using the ALERT_MASK (D8h) register.

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