LM5064PMHSLASHNOPB datasheet(19/64 Pages) TI2

19 / 64 page

UVLO/EN

SCL

PWR

VEE_K

TIMER

PGD

GATE

SDAO

SMBA

ADR0

ADR1

ADR2

VAUX

VDD

OVLO

DIODE

SDAI

VCC

OUT

RETRY

VREF

VEE

SENSE

SENSE_ K

VAUXH

OUTPUT

GND

VSYS

VDD

LM5064

LOAD

1 µF

RPWR

RPG

GND

COUT

200 k:

8.87 k:

7.87 k:

5.0SMDJ60A

3 m:

MMBT3904

FDB047N10

30.1 k:

B380-13-F

0.15 µF

100 k:

200 µF

LM5064

www.ti.com

SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013

APPLICATION INFORMATION

Figure 6. Typical Application Circuit

DESIGN-IN PROCEDURE

Refer to Figure 6 for a Typical Application Circuit. The following is a step-by-step procedure for hardware design

of the LM5064. This procedure refers to section numbers that provide detailed information on the following

design steps. The recommended design-in procedure is as follows:

MOSFET Selection: Determine the MOSFET based on breakdown voltage, current and power ratings.

Current Limit, RS: Determine the current limit threshold (ILIM). This threshold must be higher than the normal

maximum load current, allowing for tolerances in the current sense resistor value and the LM5064 Current Limit

threshold voltage. Use Equation 1 to determine the value for RS.

Power Limit Threshold: Determine the maximum allowable power dissipation for the series pass MOSFET (Q1),

using the device’s SOA information. Use Equation 2 to determine the value for RPWR. Note that many MOSFET

manufacturers do not accurately specify the device SOA so it is usually beneficial to choose a conservative value

when selecting RPWR.

Turn-on Time and TIMER Capacitor, CT: Determine the value for the timing capacitor at the TIMER pin (CT)

using Equation 7 and Equation 8. The fault timeout period (tFAULT) MUST be longer than the circuit’s turn-on time.

The turn-on time can be estimated using the equations in the TURN-ON TIME section, but should be verified

experimentally. Review the resulting insertion time and the restart timing if retry is enabled.

UVLO, OVLO: Choose option A, B, C, or D from the UVLO, OVLO section to set the UVLO and OVLO

thresholds and hysteresis. Use the procedure for the appropriate option to determine the resistor values at the

UVLO/EN and OVLO pins.

MOSFET SELECTION

It is recommended that the external MOSFET (Q1) selection is based on the following criteria:

- The BVDSS rating should be greater than the maximum system voltage (VSYS), plus ringing and transients which

can occur when the circuit card, or adjacent cards, are inserted or removed.

- The maximum continuous current rating should be based on the current limit threshold (for example, 26 mV/RS

for CL = VDD), not the maximum load current, since the circuit can operate near the current limit threshold

continuously.

- The Pulsed Drain Current spec (IDM) must be greater than the current threshold for the circuit breaker function

(49/93/187 mV/RS, depending on CL and CB configuration).

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