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LM5064PMH/NOPB Datasheet(PDF) 5 Page - Texas Instruments |
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LM5064PMH/NOPB Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 64 page ![]() LM5064 www.ti.com SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013 Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VCC-VEE = 48V. See (1) (2). Symbol Parameter Conditions Min Typ Max Units Input (VCC) IIN-EN Input current, enabled VCC - VEE = 48V, UVLO/EN = 5V 6 8 mA PORIT Threshold voltage to start VCC - VEE increasing 8 9.2 V insertion timer POREN Threshold voltage to enable VCC - VEE increasing 8.7 9.9 V all functions POREN-HYS POREN hysteresis VCC - VEE decreasing 170 mV Output (OUT) IOUT-EN OUT bias current, enabled Enabled, OUT = VEE -100 nA IOUT-DIS OUT bias current, disabled (3) Disabled, OUT = VEE + 48V 135 µA OVLO/UVLO UVLOTH UVLO/EN threshold UVLO/EN Falling 2.41 2.48 2.55 V UVLOHYS UVLO/EN hysteresis current UVLO/EN = VEE + 2V 13 20 26 µA UVLODEL UVLO delay Delay to GATE high 9 µs Delay to GATE low 12 µs UVLOBIAS UVLO/EN bias current UVLO/EN = VEE + 5V 1 µA OVLOTH OVLO threshold 2.39 2.47 2.53 V OVLOHYS OVLO hysteresis current OVLO = VEE + 2.8V -26 -21 -13 µA OVLODEL OVLO delay Delay to GATE high 10 µs Delay to GATE low 12 µs OVLOBIAS OVLO bias current OVLO = 2.3V 1 µA Power Limit (PWR) PWRLIM-1 Power limit sense voltage OUT – SENSE = 48V, RPWR = 145 k Ω 19.5 24.5 29.5 mV (OUT-SENSE) PWRLIM-2 OUT - SENSE = 24V, RPWR = 75 k Ω 24.7 mV IPWR PWR pin current VPWR = 2.5V -18 µA RSAT(PWR) PWR pin impedance when UVLO/EN = 2.0V 140 Ω disabled Gate Control (GATE) IGATE Source current Normal Operation -72 -52 -32 µA Sink current UVLO/EN < VEE+2V 3.4 4.1 5.3 mA SENSE - VEE =150 mV, VGATE =VEE+5V 50 111 180 mA VGATE Gate output voltage in normal GATE-VEE Voltage 12.6 V operation Current Limit VCL Current limit threshold voltage CL = VDD (4) 23 26 30 mV VCL Current limit threshold voltage CL = VEE or FLOAT (4) 47 50 53 mV tCL Response time SENSE-VEE stepped from 0 mV to 80 mV 54 µs ISENSE SENSE input current Enabled, OUT = VEE -5 µA Disabled, OUT = VCC -55 µA ISENSE_K SENSE_K input current -10 µA (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. (2) Current out of a pin is indicated as a negative value. (3) OUT bias current (disabled) due to leakage current through an internal 1 M Ω resistance from SENSE to OUT. (4) CL bit High or Low is set by either the CL pin on startup (if CL = VDD, then High, if CL = VEE or FLOAT, then Low) or by the current limit setting bit in the device setup register. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM5064 |
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