LM5064PMHSLASHNOPB datasheet(22/64 Pages) TI2

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VGSL

VTH

ILIM

VDS

Drain Current

VGATE

b) Power Limit and Current Limit

VGSL

VTH

ILIM

VDS

VSYS

Drain Current

VGATE

a) Current Limit Only

Gate-to-Source Voltage

VSYS

tON

Gate-to-Source Voltage

LM5064

VCC

VEE

GND

OUT

VSYS

VEE_K SENSE_K

GATE

SENSE

LM5064

VCC

VEE

GND

PGD

OUT

VSYS

VEE_K SENSE_K

GATE

SENSE

LM5064

SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013

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A. No Load Current During Turn-On

B. Load Draws Current During Turn-On

Figure 8. Current During Turn-On

B) Turn-On with Power Limit and Current Limit: The maximum allowed power dissipation in Q1 (PMOSFET(LIM))

is defined by the resistor at the PWR pin, and the current sense resistor RS. See the POWER LIMIT

THRESHOLD section. If the current limit threshold (ILIM) is higher than the current defined by the power limit

threshold at maximum VDS (PMOSFET(LIM)/|VSYS|) the circuit operates initially in the power limit mode when the VDS

of Q1 is high, and then transitions to current limit mode as the current increases to ILIM and VDS decreases.

Assuming the load (RL) is not connected during turn-on, the time for the output voltage to reach its final value is

approximately equal to:

(6)

For example, if VSYS = -48V, CL = 200 µF, ILIM = 8.7A, and PMOSFET(LIM) = 80W, tON calculates to ≊3.0 ms, and the

initial current level (IP) is approximately 1.67A. The Fault Timeout Period must be set longer than tON.

Figure 9. MOSFET Power Up Waveforms

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LM5064PMH/NOPB Datasheet(PDF) 22 Page - Texas Instruments

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