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LM5064PMH/NOPB Datasheet(PDF) 52 Page - Texas Instruments |
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LM5064PMH/NOPB Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 64 page ![]() LM5064 SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com PMBUS™ ADDRESS LINES (ADR0, ADR1, ADR2) The three address lines are to be set high (connect to VDD), low (connect to VEE), or open to select one of 27 addresses for communicating with the LM5064. Table 44 depicts 7-bit addresses (eighth bit is read/write bit): Table 44. Device Addressing ADR2 ADR1 ADR0 Decoded Address Z Z Z 40h Z Z 0 41h Z Z 1 42h Z 0 Z 43h Z 0 0 44h Z 0 1 45h Z 1 Z 46h Z 1 0 47h Z 1 1 10h 0 Z Z 11h 0 Z 0 12h 0 Z 1 13h 0 0 Z 14h 0 0 0 15h 0 0 1 16h 0 1 Z 17h 0 1 0 50h 0 1 1 51h 1 Z Z 52h 1 Z 0 53h 1 Z 1 54h 1 0 Z 55h 1 0 0 56h 1 0 1 57h 1 1 Z 58h 1 1 0 59h 1 1 1 5Ah 52 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5064 |
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