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LMK05028RGCT.B Datasheet(PDF) 21 Page - Texas Instruments |
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LMK05028RGCT.B Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 94 page  7.2 Functional Block Diagrams Input Monitors Input Monitors Ref Bypass Mux Ref Inputs System Clocks Outputs PLL Channels IN0 IN1 IN2 IN3 REF A SDA SCL GPIO1/SCS GPIO2/SDO HW_SW_CTRL PDN GPIO0/SYNCN STATUS[0:1] PLL1 ÷R VCO1: 4.8 to 5.4 GHz VCO1 FB VCO2 FB (IN5) TCXO_IN ×2 ÷M REF B PLL2 ÷R VCO2: 5.5 to 6.2 GHz VCO2 FB VCO1 FB (IN4) TCXO XO TCXO REF A REF B XO_P 0 1 2 ÷OD 20-b 0 1 2 3 ÷OD 20-b OUT7 0 1 2 3 4 5 0 1 2 3 4 5 ÷OD 20-b ÷ODB 11-b OUT1 0 1 2 3 0 1 2 3 OUT6 OUT5 OUT4 0 1 2 3 ÷OD 20-b OUT3 OUT2 OUT0 ÷OD 20-b Clock Bus Digital VDD (x9) 3.3 V VDDO (x6) 1.8 / 2.5 / 3.3 V INSEL0_[1:0] INSEL1_[1:0] SYNC DPLL1 Zero Delay Feedback I 2C/ SPI Registers EEPROM ROM Device Control and Status DPLL2 Zero Delay Feedback Power Conditioning (all blocks) CAP (3x) LF2 LF1 XO_N XO determines output jitter in 12 kHz to 20 MHz band. TCXO/OCXO determines output frequency stability. (e.g. 'f/f0 ” “4.6 ppm for SyncE) REF DPLL TCXO DPLL REF DPLL TCXO DPLL APLL APLL ÷ODB 11-b ÷OD 20-b LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock 0 1 2 3 4 5 DCO1 FDEV DCO2 FDEV ÷P1 ÷P2 ÷P1 ÷P2 Input Monitors PLL Monitors TCXO/XO Monitors OUT[4:7] OUT[0:3] Hitless Switching and Priority Selection Hitless Switching and Priority Selection Figure 7-2. Top-Level Device Block Diagram www.ti.com LMK05028 SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMK05028 |
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