LMK05028RGCT.B datasheet(13/94 Pages) TI2

13 / 94 page

Over Recommended Operating Conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Other Characteristics

tPHO

Input-to-output phase offset

Zero delay mode

PSNR

Spur induced by power supply

noise (VN = 50 mVpp)(7) (8)

VDDO_x = 2.5 V or 3.3 V, AC-DIFF or

HCSL output

-70

dBc

VDDO_x = 2.5 V, LVCMOS output

-55

PSNR

Spur induced by power supply

noise (VN = 25 mVpp)(7) (8)

VDDO_x = 1.8 V, AC-DIFF or HCSL

output

-70

VDDO_x = 1.8 V, LVCMOS output

-45

SPUR

Spur level due to output-to-output

crosstalk (adjacent channels)(8)

fOUTx = 156.25 MHz, fOUTy = 155.52

MHz, AC-DIFF or HCSL (same output

type for both channels)

-75

dBc

PLL Clock Output Performance Characteristics

RMS phase jitter

(12 kHz to 20 MHz)

156.25 MHz AC-DIFF or HCSL output,

fXO = 48.0048 MHz

150

250

fs RMS

PNTDC

Output close-in phase noise

(fOFFSET = 100 Hz)

122.88 MHz AC-DIFF or HCSL, 3-loop

mode, fXO = 48.0048 MHz, fTCXO = 10

MHz, fTCXO-TDC = 20 MHz, BWREF = 5

Hz, BWTCXO = 400 Hz

-112

dBc/Hz

DPLL bandwidth range(9)

Programmed bandwidth setting

0.01 to

4000

JPK

DPLL closed-loop jitter

peaking(14)

fIN = 25 MHz, fOUT = 10 MHz, DPLL BW

= 0.1 Hz or 10 Hz

0.1

JTOL

Jitter tolerance

Jitter modulation = 10 Hz,

25.78125 Gbps

6455

UI p-p

tHITLESS

Phase transient during hitless

switch

Valid for a single switchover event

between two clock inputs at the same

frequency

± 50

fHITLESS

Frequency transient during hitless

switch

Valid for a single switchover event

between two clock inputs at the same

frequency

± 10

ppb

tSTARTUP

Initial PLL clock start-up time(12)

From rising edge of PDN to free-

running output clocks

(1)

Total device current can be estimated by summing the individual IDD_x and IDDO_x per pin for all blocks enabled in a

given configuration.

(2)

Configuration A (All blocks on except TCXO_IN and both TCXO-DPLLs): fIN[0:3] = 25 MHz, fXO = 48.0048 MHz, TCXO_IN

disabled. Both DPLL[1:2] in 2-loop mode, fVCO1 = 5 GHz, fVCO2 = 5.5296 GHz, PLL1_P1 = 8, PLL2_P1 = 9.

(3)

Configuration B (All blocks on): fIN[0:3] = 25 MHz, fXO = 48.0048 MHz, fTCXO = 10 MHz. Both DPLL[1:2] in 3-loop mode, fVCO1 = 5 GHz,

fVCO2 = 5.5296 GHz, PLL1_P1 = 8, PLL2_P1 = 9.

(4)

Parameter is specified by characterization and is not tested in production.

(5)

For a differential input clock below 5 MHz, TI recommends to disable the differential input amplitude monitor and enable at least one

other monitor (frequency, window detectors) to validate the input clock. Otherwise, consider using an LVCMOS clock for an input

below 5 MHz.

(6)

An output frequency over the fOUT maximum specification is possible, but the output swing can be less than the VOD minimum

specification.

(7)

PSNR is the single-sideband spur level (in dBc) measured when sinusoidal noise with amplitude VN and frequency between 100 kHz

and 1 MHz is injected onto VDD and VDDO_x pins.

(8)

DJSPUR (ps pk-pk) = [2 × 10(dBc/20) / (π × fOUT) × 1E6], where dBc is the PSNR or SPUR level (in dBc) and fOUT is the output frequency

(in MHz).

(9)

Actual loop bandwidth can be lower. Applies to REF-DPLL and TCXO-DPLL. The valid loop bandwidth range can be constrained by

the DPLL loop mode and REF-TDC and/or TCXO-TDC frequencies used in a given configuration.

(10) IDDO_x includes supply current for output divider and one output driver with fOUT = 156.25 MHz or 122.88 MHz.

(11) IDDO_x includes supply current for output divider and two output drivers with fOUT = 156.25 MHz or 122.88 MHz.

(12) Assumes XO input clock is stable in frequency and amplitude before rising edge of PDN, PLLs start-up using parallel calibration mode,

VCO wait timers set to 0.4 ms, PLL wait timers set to 3 ms, and outputs auto-mute during APLL lock only (DPLL auto-mute options

disabled).

(13) Parameter is specified for PLL outputs divided from either VCO domain.

(14) The TICS Pro software configures the closed-loop jitter peaking for 0.1 dB or less based on the programmed DPLL bandwidth setting.

(15) Minimum limit applies for the minimum setting of the differential input amplitude monitor.

www.ti.com

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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