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LMK05028RGCT.B Datasheet(PDF) 24 Page - Texas Instruments

Part # LMK05028RGCT.B
Description  LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM
PDF  94 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

LMK05028RGCT.B Datasheet(HTML) 24 Page - Texas Instruments

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1. Below BWREF-DPLL, the REF input noise contributes to output.
2. Above BWREF-DPLL, the REF input noise is attenuated by REF-DPLL bandwidth with up to 60-dB/decade
roll-off.
3. Below BWTCXO-DPLL, the OCXO noise and TDC noise of the TCXO-DPLL determine the output noise here.
The close-in phase noise is –112 dBc/Hz at 100-Hz offset.
4. Above BWTCXO-DPLL, the OCXO noise is attenuated. Below BWAPLL, the APLL noise dominates as the XO
noise contribution is much lower.
5. Above BWAPLL, the VCO noise dominates and the XO noise is attenuated.
6. AC-LVPECL output noise floor is -163 dBc/Hz at 10-MHz offset.
BW
REF-DPLL
5 Hz
BW
TCXO-DPLL
400 Hz
BW
APLL
500 kHz
1
2
3
4
5
6
Output Phase Jitter = 160-fs RMS (12 kHz to 20 MHz)
AC-LVPECL output, fIN = 25 MHz, fTCXO = 10 MHz (OCXO), fXO = 48.0048 MHz, fTCXO-TDC = 20 MHz
Figure 7-5. 122.88-MHz Output Phase Noise (3-Loop) With Phase Noise of External Inputs
LMK05028
SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025
www.ti.com
24
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Copyright © 2025 Texas Instruments Incorporated
Product Folder Links: LMK05028



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