LMK05028RGCT.B datasheet(49/94 Pages) TI2

49 / 94 page

7.3.13.1 AC-Differential Output (AC-DIFF)

The differential output driver uses a switched-current mode type shown in Figure 7-28. A programmable tail

current of 4, 6, or 8 mA (nominal) is used to achieve VOD swing compatible with AC-coupled LVDS, CML,

or LVPECL receivers, respectively, across a 100-Ω differential termination. The differential output driver is

ground-referenced (similar to a HCSL driver), meaning the differential output has a low common-mode voltage

(VOS).

The differential driver is internally biased and does not need any external pullup or pulldown resistors, unlike

conventional CML or LVPECL drivers. The differential output must be interfaced through external AC-coupling to

a differential receiver with proper input termination and biasing.

Output tail current (I1 + I2) can be programmed

to 4, 6, or 8 mA for LVDS-, CML-, and LVPECL-

compatible swing across AC-coupled

50-: single-ended or 100-: differential load.

OUTx_P

OUTx_N

VDDO_x

clk_p

clk_n

I1 = 4 mA

I2 = 0, 2, or 4 mA

LDO

From

output

channel

Figure 7-28. AC-LVDS/CML/LVPECL Output Driver Structure

7.3.13.2 HCSL Output

The HCSL output driver is an open-drain type, which must be DC-coupled to an HCSL receiver. The HCSL

output has programmable, internal 50-Ω to ground (on P and N) for source termination, which can be enabled

when the receiver does not provide input (load) termination. If the internal termination is disabled, external 50-Ω

termination to ground (on P and N) is required at either the driver side (source terminated) or receiver side (load

terminated).

7.3.13.3 LVCMOS Output (1.8 V, 2.5 V)

The LVCMOS driver has two outputs per pair. Each output on P and N can be configured for normal polarity,

inverted polarity, or disabled as HiZ or static low level. The LVCMOS output high level (VOH) is determined by the

VDDO_x voltage of 1.8 V or 2.5 V for rail-to-rail LVCMOS output voltage swing. If a VDDO_x voltage of 3.3 V

is applied, the VOH level does not swing to the VDDO_x rail due to the dropout voltage of the channel's internal

LDO regulator.

Because an LVCMOS output clock is a high-swing and unbalanced signal, the clock can be a strong aggressor

and couple noise onto other jitter-sensitive differential output clocks. If an LVCMOS clock is required from an

output pair, configure the pair with both outputs enabled but with opposite polarity (+/– or –/+) and leave the

unused output floating with no trace connected.

7.3.13.4 Output Auto-Mute During LOL or LOS

Each output driver can automatically mute or squelch the clock when the selected output mux clock source is

invalid, as configured by the CH_x_MUTE bit. If the selected clock source is derived from a PLL post-divider

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LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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