LMK05028RGCT.B datasheet(45/94 Pages) TI2

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7.3.9.9 REF-DPLL Reference Divider (R)

The reference clock input paths to each REF-DPLL features a 16-b reference divider (R) for each clock input

(IN0 to IN3). The output of each R divider sets the frequencies to the reference input mux and the TDC rate

of the REF-DPLL. There are also two additional R dividers for the internal VCO loopback clocks (IN4 and IN5)

that can be used in cascaded PLL configurations. IN4 refers to the VCO1 loopback clock to DPLL2 reference

input, and IN5 refers to the VCO2 loopback clock to DPLL1 reference input. To support hitless switching between

inputs with different frequencies, the R divider can be used to divide the clocks to a single common frequency to

the REF-DPLL TDC input.

7.3.9.10 TCXO/OCXO Input Doubler and M Divider

The TCXO/OCXO input features a frequency doubler followed by a 5-b M divider. The M divider output is sent to

the TCXO mux of both TCXO-DPLLs.

7.3.9.11 TCXO Mux

Each PLL channel has a TCXO mux to select the TCXO-DPLL input from either the TCXO M divider clock, or the

VCO loopback clock from the opposite PLL channel when PLL cascading is used. When the TCXO M divider is

selected, the M Divider frequency sets the TCXO-TDC rate. When the VCO loopback clock is selected, the VCO

loopback divider frequency from the opposite PLL sets the TCXO-TDC rate.

7.3.9.12 REF-DPLL and TCXO-DPLL Time-to-Digital Converter (TDC)

The TDCs for the REF-DPLL and TCXO-DPLL operate up 30 MHz. The TDC resolution is fine enough to

achieve in-band phase noise of –112 dBc/Hz at 100-Hz offset for a 122.88-MHz output.

When the REF mux selects a reference input clock, the REF-DPLL TDC rate is:

fREF-TDC = fINx / RINx

(10)

When the REF mux selects the VCO loopback clock, the REF-DPLL TDC rate is:

fREF-TDC = fVCOa / (48 × DIVDPLLa_CLK_FB) / RINx

(11)

When the TCXO mux selects the M divider clock, the TCXO-DPLL TDC rate is:

fTCXO-TDC = fTCXO × DTCXO / MTCXO

(12)

When the TCXO mux selects the VCO loopback clock, the TCXO-DPLL TDC rate is:

fTCXO-TDC = fVCOa / (48 × DIVDPLLa_CLK_FB)

(13)

where

• fVCOa: VCO frequency fed back from the first PLL channel (PLLa) in a cascaded configuration

• DIVDPLLy_CLK_FB: VCO loopback divide value (3 to 32) from PLLa

7.3.9.13 REF-DPLL and TCXO-DPLL Loop Filter

Each REF-DPLL and TCXO-DPLL supports programmable loop bandwidth from 10 mHz to 4 kHz and can

achieve jitter peaking below 0.1 dB (typical). The low-pass jitter transfer characteristic of each DPLL attenuates

the reference input noise with up to 60-dB/decade roll-off above the loop bandwidth.

In 3-loop mode, the REF-DPLL loop filter output modulates the TCXO-DPLL SDM, and the TCXO-DPLL loop

filter output correspondingly modulates the APLL SDM to steer the APLL VCO into lock with the selected

REF-DPLL input.

In 2-loop REF-DPLL mode, the TCXO-DPLL is not used and the REF-DPLL loop filter output controls the APLL

SDM to steer the VCO frequency into lock with the selected REF-DPLL input.

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LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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