LMK05028RGCT.B datasheet(32/94 Pages) TI2

32 / 94 page

LVDS Driver

LVDS

LMK05028

100

Figure 7-15. DC-Coupled LVDS to Reference (INx) or XO Inputs

CML

Driver

CML

LMK05028

Figure 7-16. DC-Coupled CML (Source Terminated) to Reference (INx) or XO Inputs

LMK05028

HCSL

Driver

HCSL

Figure 7-17. HCSL (Load Terminated) to Reference (INx) or XO Inputs

Differential

Driver

LMK05028

100

Internal input biasing

Driver

LVDS

CML*

3.3-V LVPECL

2.5-V LVPECL

HCSL

RB ( )

open

150

*CML driver has 50-

pull-up

Figure 7-18. AC-Coupled Differential to Reference (INx) or XO Inputs

7.3.5 Reference Input Mux Selection

For each REF-DPLL block, the reference input mux selection can be done automatically using an internal state

machine with a configurable input priority scheme, or manually through software register control or hardware pin

control. The input mux can select from IN0 to IN3. Additionally, DPLL1 can select IN5 as an internal loopback

clock divided-down from PLL2 VCO (VCO2 FB clock), and DPLL2 can select IN4 as an internal loopback clock

from PLL1's VCO (VCO1 FB clock).

The priority for all inputs can be assigned for each DPLL through registers. The priority ranges from 0 to 6,

where 0 means Ignored (never select) and 1 to 6 are highest (1st) to lowest (6th) priority. When two or more

inputs are configured with the same priority setting, the reference input with the lowest index (INx) is given higher

priority.

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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