LMK05028RGCT.B datasheet(43/94 Pages) TI2

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Equation 5, Equation 6, Equation 7, Equation 8, and Equation 9 relate to the output frequency according to the

output channel mux selection (CHxMUX).

fCHxMUX = fVCOy / PnPLLy when PLLy post-divider is selected

(5)

fCHxMUX = fXO when XO is selected (OUT0 or OUT1)

(6)

fCHxMUX = fTCXO/REF when TCXO or REF is selected (OUT0 or OUT1)

(7)

fOUTx = fCHxMUX / ODOUTx (OUT1 to OUT6)

(8)

fOUTx = fCHxMUX / (DIVAOUTx × DIVBOUTx) (OUT0 or OUT7 only)

(9)

where

• fCHxMUX: Output channel mux frequency (from PLL post-divider, XO, or TCXO/Ref Bypass mux)

• fTCXO/REF: TCXO, DPLL1 Ref, or DPLL2 Ref input frequency (selected by TCXO/Ref Bypass mux)

• fOUTx: Output clock frequency (x = 0 to 7)

• PnPLLy: PLLy P1 (primary) or P2 (secondary) post-divider value (4 to 9, 11, 13)

• ODOUTx: Output divide value (20 bits, 1 to 220-1)

• ODBOUTx: Output MSB divide value for OUT0 or OUT7 (11 bits, 1 to 211-1)

7.3.9.2 Analog PLL (APLL)

The APLL has a 40-bit fractional-N divider to support high-resolution frequency synthesis, wide output frequency

range, very low phase noise and jitter, and the ability to tune the VCO frequency through sigma-delta modulator

(SDM) control.

The APLL XO doubler doubles the XO input frequency into the phase frequency detector (PFD) input. The APLL

multiplies the PFD frequency by the total N divider value to generate the VCO clock. The desired VCO output

to PFD input frequency ratio is the total value of N (INT + NUM/DEN) applied to the SDM to tune the VCO

frequency.

In free-run mode, the APLL uses a low-jitter XO input as a initial reference clock to lock the internal voltage

controlled oscillator (VCO). The PFD compares the fractional-N divided clock with the XO doubler frequency

and generates a control signal. The control signal is filtered by the APLL loop filter to generate the VCO control

voltage that sets the output frequency. The SDM modulates the N divider ratio to get the desired fractional ratio

between the PFD input and the VCO output.

In 2-loop or 3-loop mode, the APLL SDM is controlled by one of the DPLL loops to pull the VCO frequency into

lock with the DPLL reference input.

7.3.9.3 APLL XO Doubler

The APLL has a XO doubler that can be enabled to double the PFD frequency up to 200 MHz. The doubler

adds minimal noise and is useful for raising the PFD frequency for better phase noise and jitter and also to avoid

spurs. When the PFD frequency is increased, the flat portion of the APLL phase noise improves.

7.3.9.4 APLL Phase Frequency Detector (PFD) and Charge Pump

The APLL PFD frequency can operate from 10 MHz to 200 MHz, but the APLL performance is optimized for

frequencies of 96 MHz or higher. The PLL has programmable charge pump settings of 1.6, 3.2, 4.8, or 6.4 mA.

7.3.9.5 APLL Loop Filter

The APLL supports programmable loop bandwidth from 100 kHz and 1 MHz. The loop filter components can be

programmed to optimize the APLL bandwidth depending on the XO frequency and phase noise without changing

any external components. The LF1 and LF2 pins each require an external C2 capacitor to ground, typically

0.1-µF. Figure 7-26 shows the APLL loop filter structure between the PFD/charge pump output and VCO control

input.

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LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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