LMK05028RGCT.B datasheet(52/94 Pages) TI2

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The following requirements must be met establish a SYNC group for two or more output channels:

• Output dividers have the respective sync enabled (CHx_SYNCEN bit = 1).

• Output dividers have the output mux selecting the same PLL primary post-divider (for example, PLL1 P1 or

PRI, PLL1 P2 or SEC).

• The PLL post-divider (PRI or SEC) must have the applicable sync bank bits enabled for the output divider

banks. Examples:

– PLL1_PRI_CH47_SYNC_BANK must be set when output dividers in OUT[4:7] bank is synced to PLL1 P1

(PRI).

– PLL1_SEC_CH03_SYNC_BANK must be set when output dividers in OUT[0:3] bank is synced to PLL1

P1 (SEC).

A SYNC event can be asserted by the hardware GPIO0/SYNCN pin (active low) or the SYNC_SW register bit

(active high). When SYNC is asserted, the SYNC-enabled dividers held are reset and clock outputs are muted.

The divider reset and output muting is done synchronously, allowing the outputs to finish the final clock cycle (to

avoid a short clock period) before the actual SYNC event. When SYNC is deasserted, the outputs starts with

the initial clock phases synchronized or aligned. SYNC can also be used to mute any SYNC-enabled outputs to

prevent output clocks from being distributed to down-stream devices until the devices are configured and ready

to accept the incoming clock. The SYNC signal is internally qualified or sampled by the internal digital system

clock that runs at 10 MHz nominal. The negative pulse applied to the SYNCN input pin must be greater than 200

ns to be captured by the internal digital system clock. SYNC deassertion can take two cycles of the digital clock

before the outputs are released.

Output channels with the sync disabled (CHx_SYNCEN bit = 0) is not affected by a SYNC event and continues

normal output operation as configured. Also, VCO and PLL post-divider clocks do not stop running during the

SYNC so the clocks can continue to source any output channels that do not require synchronization. Output

dividers with divide-by-1 (divider bypass mode) are not gated during the SYNC event. Also, SYNC must be

disabled and is not supported when the output mux is selecting the XO, TCXO, or DPLL reference clocks.

Table 7-9. Output Synchronization

GPIO0 PIN

SYNC_SW BIT

OUTPUT DIVIDER AND DRIVER STATE

Output drivers muted and output dividers reset

0→1

1→0

Outputs in a SYNC group are unmuted with the initial clock phases aligned

Normal output driver/divider operation as configured

Figure 7-34 shows an example of the SYNC timing example for a SYNC group. The SYNC group is comprised

of OUT0, OUT6, and OUT7 dividers, which are sourced by the PLL1 P1 (primary) post-divider. Notice that the

output divider reset and output mute is applied synchronously by waiting until the last output clock in the group

goes low (OUT7).

Internal SYNC starts and waits for last output in the

³6<1& JURXS´ WR JR ORZ EHIRUH 6WHS

Dividers SYNCed and drivers muted. Each

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SYNCed dividers released.

PLL Post Divider

Output Channel Dividers

SYNCed outputs muted

VCO

PLL1_P1 = 4

(Primary Post-div)

OUT0_DIV = 4

OUT6_DIV = 5

OUT7_DIV = 6

Internal SYNC

(Qualified by

Digital clock)

Up to 2 Digital clock cycles

OUT[0,6,7] FRQVWLWXWH D ³6<1& JURXS´ E\ VHOHFWLQJ WKH VDPH 3//1_P1 post-divider with its SYNC Banks enabled (PLL1_PRI_CHx_SYNC_BANK = 1) and by having their respective channel SYNC enabled (CHx_SYNC_EN = 1).

Phase Aligned

The VCO clock and PLL post-divider clock do not stop running during the SYNC.

Figure 7-34. Output SYNC Group Timing Example

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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