LMK05028RGCT.B datasheet(28/94 Pages) TI2

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7.3 Feature Description

The following sections describe the features and functional blocks of the LMK05028.

7.3.1 Oscillator Input (XO_P/N)

The XO input is the reference clock for the fractional-N APLLs. The combination of XO and APLL determines the

jitter and phase noise performance of the output clocks. For optimal performance, the XO frequency must be at

least 48 MHz and have a non-integer frequency relationship with the VCO frequencies so the APLLs operate in

fractional mode. When the TCXO input is not used by either PLL channel, the XO input determines the output

frequency accuracy and stability in free-run or holdover modes.

The XO input buffer has programmable input on-chip termination and AC-coupled input biasing configurations as

shown in Figure 7-8.

The buffered XO path also drives the input monitoring blocks as well as output muxes, allowing buffered copies

of the XO input on OUT0 and/or OUT1.

LMK05028

Differential or

Single-Ended*

28 pF

100

100 k

VAC-DIFF

(weak bias)

100 k

28 pF

XO_P

XO_ N

XO path

*Supports 2.5-V

single-ended swing

Figure 7-8. XO Input Buffer

Table 7-3 lists the typical XO input buffer configurations for common clock interface types.

Table 7-3. XO Input Buffer Modes

XO_DIFF_TYPE

INPUT TYPES

INTERNAL SWITCH SETTINGS

INTERNAL TERM. (S1, S2)(1)

INTERNAL BIAS (S3)(2)

LVDS, CML, LVPECL, LVCMOS

(DC-coupled)

OFF

LVDS, CML, LVPECL

(AC-coupled)

OFF

ON (1.3 V)

LVDS, CML, LVPECL

(AC-coupled, internal 100-Ω)

100 Ω

ON (1.3 V)

HCSL

(DC-coupled, internal 50-Ω)

50 Ω

OFF

(1)

S1, S2: OFF = External termination is assumed.

(2)

S3: OFF = External input bias or DC coupling is assumed.

7.3.2 TCXO/OCXO Input (TCXO_IN)

The TCXO input is the reference clock to the TCXO-DPLL loop in each PLL channel. When the PLL channel

uses the TCXO-DPLL, the TCXO input source determines the close-in phase noise and wander performance

(MTIE/TDEV) when the DPLL is locked, as well as the frequency accuracy and stability in free-run and

holdover modes. A TCXO input with high phase noise floor must have minimal or no impact on the output jitter

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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