M25PX64-STVMF6F datasheet(38/66 Pages) NUMONYX

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Instructions

M25PX64

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6.8

Dual output fast read (DOFR)

The dual output fast read (DOFR) instruction is very similar to the read data bytes at higher

speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin DQ0

and pin DQ1) instead of only one. Outputting the data on two pins instead of one doubles

the data transfer bandwidth compared to the read data bytes at higher speed (FAST_READ)

instruction.

The device is first selected by driving Chip Select (S) Low. The instruction code for the dual

output fast read instruction is followed by a 3-byte address (A23-A0) and a dummy byte,

each bit being latched-in during the rising edge of Serial Clock (C). Then the memory

contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency fC,

during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 15.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole

memory can, therefore, be read with a single dual output fast read (DOFR) instruction.

When the highest address is reached, the address counter rolls over to 00 0000h, so that

the read sequence can be continued indefinitely.

Figure 15.

Dual output fast read instruction sequence

Address bit A23 is don’t care.

456789 10

28 29 30 31

23 22 21

Mode 3

Mode 2

DQ0

DQ1

High Impedance

Instruction

24-bit address (1)

DQ0

DQ1

32 33 34

36 37 38 39 40 41 42 43 44 45 46

753175

DATA OUT 1

Dummy byte

MSB

531

7531

MSB

6420

642064

MSB

DATA OUT 2

DATA OUT 3

DATA OUT n

ai13574b

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