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M25PX64-STVMF6F Datasheet(PDF) 17 Page - Numonyx B.V |
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M25PX64-STVMF6F Datasheet(HTML) 17 Page - Numonyx B.V |
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17 / 66 page ![]() M25PX64 Operating features 17/66 As a second level of protection, the Write Protect signal (applied on the W/VPP pin) can freeze the status register in a read-only mode. In this mode, the block protect bits (BP2, BP1, BP0) and the status register write disable bit (SRWD) are protected. For more details, see Section 6.5: Write status register (WRSR). Table 3. Protected area sizes Status register contents Memory content TB bit BP bit 2 BP bit 1 BP bit 0 Protected area Unprotected area 0 0 0 0 none All sectors(1) (128 sectors: 0 to 127) 0 0 0 1 Upper 64th (2 sectors: 126 and 127) Lower 63/64ths (126 sectors: 0 to 125) 0 0 1 0 Upper 32nd (4 sectors: 124 to 127) Lower 31/32nds (124 sectors: 0 to 123) 0 0 1 1 Upper 16th (8 sectors: 120 to 127) Lower 15/16ths (120 sectors: 0 to 119) 0 1 0 0 Upper 8th (16 sectors: 56 to 63) Lower 7/8ths (112 sectors: 0 to 111) 0 1 0 1 Upper quarter (32 sectors: 96 to 127) Lower three-quarters (96 sectors: 0 to 95) 0 1 1 0 Upper half (64 sectors: 64 to 127) Lower half (64 sectors: 0 to 63) 0 1 1 1 All sectors (128 sectors: 0 to 127) none 1 0 0 0 none All sectors(1) (128 sectors: 0 to 128) 1 0 0 1 Lower 64th (2 sectors: 0 to1) Upper 63/64ths (126 sectors: 2 to 127) 1 0 1 0 Lower 32nd (4 sectors: 0 to 3) Upper 31/32nds (124 sectors: 4 to 127) 1 0 1 1 Lower 16th (8 sectors: 0 to 7) Upper 15/16ths (120 sectors: 8 to 127) 1 1 0 0 Lower 8th (16 sectors: 0 to15) Upper 7/8ths (112 sectors: 16 to 127) 1 1 0 1 Lower 4th (32 sectors: 0 to 31) Upper 3/4ths (96 sectors: 32 to 127) 1 1 1 0 Lower half (64 sectors: 0 to 63) Upper half (64 sectors: 64 to 127) 1 1 1 1 All sectors (128 sectors: 0 to 127) none 1. The device is ready to accept a bulk erase instruction if, and only if, all block protect (BP2, BP1, BP0) are 0. |
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