M25PX64-STVMF6F datasheet(29/66 Pages) NUMONYX

Part #	M25PX64-STVMF6F

Description	64-Mbit, dual I/O, 4-Kbyte subsector erase, serial flash memory with 75 MHz SPI bus interface

PDF	66 Pages

Scroll/Zoom	100%

Manufacturer	NUMONYX [Numonyx B.V]

Direct Link	http://www.numonyx.com

Logo

29 / 66 page

M25PX64

Instructions

29/66

6.2

Write disable (WRDI)

The write disable (WRDI) instruction (Figure 9) resets the write enable latch (WEL) bit.

The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The write enable latch (WEL) bit is reset under the following conditions:

●

Power-up

●

Write disable (WRDI) instruction completion

●

Write status register (WRSR) instruction completion

●

Write to lock register (WRLR) instruction completion

●

Page program (PP) instruction completion

●

Dual input fast program (DIFP) instruction completion

●

Program OTP (POTP) instruction completion

●

Subsector erase (SSE) instruction completion

●

Sector erase (SE) instruction completion

●

Bulk erase (BE) instruction completion

Figure 9.

Write disable (WRDI) instruction sequence

DQ0

AI13732

DQ1

34567

High Impedance

Instruction

M25PX64-STVMF6F Datasheet(PDF) 29 Page - Numonyx B.V