M25PX64-STVMF6F datasheet(32/66 Pages) NUMONYX

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Instructions

M25PX64

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6.4

Read status register (RDSR)

The read status register (RDSR) instruction allows the status register to be read. The status

is in progress. When one of these cycles is in progress, it is recommended to check the

write in progress (WIP) bit before sending a new instruction to the device. It is also possible

to read the status register continuously, as shown in Figure 11.

The status and control bits of the status register are as follows:

6.4.1

WIP bit

The write in progress (WIP) bit indicates whether the memory is busy with a write status

‘0’ no such cycle is in progress.

6.4.2

WEL bit

The write enable latch (WEL) bit indicates the status of the internal write enable latch. When

set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is

reset and no write status register, program or erase instruction is accepted.

6.4.3

BP2, BP1, BP0 bits

The block protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to

be software protected against program and erase instructions. These bits are written with

the write status register (WRSR) instruction. When one or more of the block protect (BP2,

BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in Table 3) becomes

protected against page program (PP) and sector erase (SE) instructions. The block protect

(BP2, BP1, BP0) bits can be written provided that the hardware protected mode has not

been set. The bulk erase (BE) instruction is executed if, and only if, all block protect (BP2,

BP1, BP0) bits are 0.

Table 7.

Status register format

SRWD

BP2

BP1

BP0

WEL

WIP

Status register write protect

Top/bottom bit

Block protect bits

Write enable latch bit

Write in progress bit

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